Saturday 14 April 2018

PSoC 4 Bootloader UDB vs SCB Speeds

Summary
This purpose of this blog was to test and verify, partially for my own curiosity, the download speeds of I2C, UART and UART operating as RS485 for the PSoC 4 using UDB and SCB type components. Operating the SCB UART in RS485 was not possible as an out of box setup, so this test was omitted.

Test Hardware
A Cypress PSoC development kit CY8CKIT-042 was configured to use the on-board I2C, UART or UART (RS485) using UDB and SCB components.

CY8CKIT-042
CY8CKIT-042 - Courtesy Cypress Semiconductor

For UART testing, a separate USB to Serial converter by 
Prolific was utilised. The model from Adafruit for instance was USB to TTL Serial Cable - Debug / Console Cable for Raspberry Pi. For connecting the TTL end of the Prolific cable, the Black wire was connected to 0V, White to pin P0.5 and Green to pin P0.4 of the Cypress Development Kit.


Prolific USB to TLL Converter
Prolific USB to TLL Converter

Similarly a USB to RS485 converter by FTDI was used in conjunction with a LinkSprite RS485 Rev1 adaptor board to connect between the target PC and the Cypress development board. Some hardware modifications were required on the earlier model LinkSprite for use with the Cypress Development board. These changes were related to the Receive and Transmit Enable lines which needed to be driven from the PSoC using the UDB components TX Enable output. The following link LinkSprite RS485.pdf, shows the modifications made to the LinkSprite Rev 1 board.

FTDI USB-RS485-WE-1800-BT
FTDI USB-RS485-WE-1800-BT

LinkSprite (RS485) Fitted to PSoC Development Board
LinkSprite (RS485) Fitted to PSoC Development Board

From the FTDI RS485 adaptor to the LinkSprite only the Data+ and Data- connections were used, which corresponds to the Orange and Yellow wires, as shown in the image above.

Test Software
An application for the DS18B20 OneWire bus was converted into a bootloadable project for testing. Any project could have been used, this was handy at the time. It should be noted that the programming file .CYACD used for testing was less than 20kb.

As mentioned in the blog introduction, both UDB and SCB communications solutions were tested. Where possible the Cypress project and components were left with minimal changes. Clocks with fractional dividers were used to achieve the best tolerance for the communications rates. Note that other methods of deriving the most desirable clock for the given baud rate were not tried - only minimal changes were made to the project.

Some notes on the testing performed.

Reference Download I2C
In most instances, when using a 042 Cypress Development Kit, the Kitprog hardware interface is used to update the target PSoC device from PSoC Creator. The time to perform an update could be determined from PSoC Creator although it would be unlikely that a field solution would use a Kitprog interface for updating the PSoC. I2C was therefore used as the reference for download speeds on this development kit.

Cypress Windows Bootloader Host
For all of the downloads performed, the Cypress Bootloader Host was used from within PSoC Creator. The Cypress UART Bootloader application does not support baud rates above 115200 at the time of writing.


Cypress Bootloader Host
Cypress Bootloader Host
Baud Rate Clocks (SCB)
The clocks shown below were used for UART testing, with the oversampling setting left at the default of 12, for a range from 57,600 to 921600 baud. This was implemented due to the warning raised by PSoC Creator relating to clock accuracy. All rates below 57,600 did not show a warning relating to tolerance.


PSoC Creator Clock Tolerance Warning
PSoC Creator Clock Tolerance Warning


SCB UART 56,700 Clock Input
SCB UART 56,700 Clock Input


SCB UART 115,200 Clock Input
SCB UART 115,200 Clock Input


SCB UART 230,400 Clock Input
SCB UART 230,400 Clock Input
SCB UART 460,800 Clock Input
SCB UART 460,800 Clock Input
SCB UART 921,600 Clock Input
SCB UART 921,600 Clock Input
Baud Rate Clocks (UDB)
The clocks shown below were used for UART testing from 460,800 to 921600 baud. All rates below 460,800 did not show a tolerance warning.


UDB UART 460,800 Clock Input
UDB UART 460,800 Clock Input
UDB UART 921,600 Clock Input
UDB UART 921,600 Clock Input

I2C Configuration
For the I2C (not EZI2C) the data rates were changed from 50 to 1000kbps in the PSoC Creator component.


PSoC Creator I2C Component Bootloader Configuration
PSoC Creator I2C Component Bootloader Configuration
A corresponding change was made to the Bootloader Host application to match the data rate - example capture of the 1000kbps shown below..


PSoC Creator Bootloader Host I2C 1000kbps
PSoC Creator Bootloader Host I2C 1000kbps
UART Configuration
The UART was configured in the same manner for the UDB and SCB components with the exception of the RS485 TX Enable line which is not available on the SCB component for the PSoC4.


UART SCB Component Basic Configuration
UART SCB Component Basic Configuration
UART SCB Component Advanced Configuration
UART SCB Component Advanced Configuration
The oversampling setting was unchanged at 12 and the Tx and Rx buffer were configured for 64 bytes as required for the Bootloader component.


UART UDB Component Configuration
UART UDB Component Configuration
UART UDB Component Advanced Configuration
UART UDB Component Advanced Configuration
For the UDB component the Tx and Rx buffer were configured for 64 bytes as required for the Bootloader component. When required, the hardware TX Enable output was enable in the UDB component.

Test Results
After all the setup detail above, the results recorded from the Cypress Bootloader application with a PSoC 4 are listed in the table below.


Cypress Bootloader Download Times for UDB and SCB Components
Cypress Bootloader Download Times for UDB and SCB Components
The same tests were conducted several times and it should be noted that there was some variation in the results. As a percentage the variation was no more than five percent.

Graphing the recorded results listed above, the shortest time for download is easily visible, the SCB UART. Coming in a close second is the I2C connection seen on most Cypress development kits. The results do show how dedicated hardware on the PSoC 4 performs notably better than Universal Digital Blocks (UDB).


Graphed Cypress Bootloader Download Times for UDB and SCB Components
Graphed Cypress Bootloader Download Times for UDB and SCB Components
Code and Project
The code snippet for the Bootloader application is listed below.

/* ========================================
 *  Shell code for running the bootloader
 * ========================================
*/

#include "project.h"

int main(void)
{
    CyGlobalIntEnable;      /* Enable global interrupts. */   
    Bootloader_Start();     /* Start bootloader, wait forever */

    for(;;)
    {
    }
}

/* [] END OF FILE */ 

Lastly the project itself which contains the Bootloader and Bootloadable applications.


Bootloader - Bootloadable Test Application
Bootloader - Bootloadable Test Application




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