Showing posts with label bootloader. Show all posts
Showing posts with label bootloader. Show all posts

Thursday, 13 June 2019

PSoC5 Dual Application USB FS Bootloader

Summary
This post provides an example Cypress bootloader project which features dual bootloadable applications and updates through USB communications.

Why an Example
While looking into field upgrades for Cypress microcontrollers, it was found that the MiniProg3, Kitprog boards with snap off programming modules or a Cypress bootloader were commonly used in the example projects. This was no doubt a small portion of what is available but not what was required. Some examples featured a bootloader and a single application although none were published with dual applications.

Looking at the newer range of Cypress devices, there were dual application bootloader examples for the PSoC6 MCU however these examples were not portable back to the PSoC4 or PSoC5 devices.

Using a PSoC5 development board and related Cypress documentation, a project with basic bootloader and bootloader functionality was created.

Development Board
For this post the Cypress PSoC5 CY8CKIT-059 was used for testing dual application functionality. One hardware modification was made for detecting when USB power was applied to the Micro USB connector. The Micro USB connector is shown to the left side of the PSoC5 development board in the image below.


PSoC5 Test Setup
PSoC5 Test Setup
 
Bootloader Setup and Hardware Changes
The Cypress code example, USBFS_Bootloader.cywrk, served as the framework for the dual application project. 

As a first step the example projects reference PSoC device, CY8C3866AXI, was changed to a CY8C5888LTI-LP097 to suit the PSoC5 development board.

Opening the USBFS component the name of the USB descriptor string was changed under the String Descriptor tab to reflect the PSoC5 device.


USBFS String Descriptor Change
USBFS String Descriptor Change
 
Under the Advanced tab of the USBFS component, the VBUS option was enabled. This input facilitates detection of USB power through a physical input on the PSoC5. Enabling the VBUS (input) in the USBFS component was not mandatory. The input serves two purposes, firstly the USBFS component can return the state of the USB power using the API - USBFS_VBusPresent(). Secondly the USB power (Micro USB connector) detection allows one possible method of initiating the Cypress bootloader when the device is bus powered.


USBFS VBUS Monitoring
USBFS VBUS Monitoring
 
With VBUS monitoring enabled in the USBFS component, an input was available on the component.
USBFS VBUS Monitor Input
USBFS VBUS Monitor Input
 
As shown in the capture above, input P15_5 was connected to the component for USB power detection.

On the rear of the development board a wire link was made between the P15_5 pad and the Anode of component D2.


PSoC5 USB Bus to VBUS Input
PSoC5 USB Bus to VBUS Input
 
Shown below is a portions of the PSoC5 development board schematic (Micro USB connector). The wire link connected from P15_5 to the Anode of D2 was made to ensure that USB (Micro USB connector) power was detected and not the power provided by the usual KitProg connector.



In the Bootloader component the wait for command was reduced to a time of zero so that the Application 1 or 2 could be called by the bootloader. The dual application and golden image support was also enabled. Golden image support was enabled in the Bootloader component to ensure that a valid Application 1 would always be available. It should be noted that the project will operate with only Application 2 programmed. Changes could be made in the firmware to prevent this operation.


Bootloader Component Configuration
Bootloader Component Configuration
 
A timer for flashing an LED and UART for debugging were also added to the project. These items were not critical for operation.

Bootloadable Setup
The bootloadable firmware (Applications) were essentially the same. These projects consisted of a Bootloadable component and each with a timer for flashing a LED. The difference between the two applications were the different LED flashing rates.


Bootloadable Component Configuration
Bootloadable Component Configuration

For the settings in the Bootloadable component, it was stated on page 44 of the Cypress Bootloader and Bootloadable component datasheet that the Manual application image placement information for the dual applications should be the same.


Bootloader and Bootloadable Component Datasheet - Extract Page 44
Bootloader and Bootloadable Component Datasheet - Extract Page 44
The bootloadable dependencies (.hex and .elf) for the two applications was referenced to the projects bootloader.


Bootloadable Projects Bootloader Dependency
Bootloadable Projects Bootloader Dependency 
 
Bootloader Firmware 
For the Bootloader firmware, a check was added for the USB (Micro USB connector) power using the call USBFS_VBusPresent(). 

If the Micro USB power was detected then the Cypress Bootloader was initiated.
To update Bootloadable Application 2 over USB, a call using Bootloader_SetActiveAppInMetadata(0) was required.

Otherwise without Micro USB power the bootloadable applications were verified using the call Bootloader_ValidateBootloadable(). Switching to a valid Bootloadable application was made with application 2 taking precedence over application 1.

/**
* @file main.c
*
* @version 1.0
*
* @brief Shell example for Cypress Dual Application Bootloadable project                                      
*/

#include <project.h>
#include <stdbool.h>
#include <Bootloader.c>             /* Required to set active app in metadata */

CY_ISR_PROTO(SYS_TMR_HANDLER);
/**
* @brief System timer, flashes LED
*/
CY_ISR(SYS_TMR_HANDLER)
{   
    LED_Write(~LED_Read());
    Timer_2_ReadStatusRegister();
    isr_SysTmr_ClearPending();   
}

/**
* @brief Boot to valid APP2 then APP1 if no VBUS.
* @details VBUS present allow bootloader
*/
int main(void)
{
    CyGlobalIntEnable;
    isr_SysTmr_StartEx(SYS_TMR_HANDLER);
    UART_Start();
    USBFS_Start(0, USBFS_5V_OPERATION);

    if (USBFS_VBusPresent() == true)
    {
       LED_Write(true);
       Bootloader_SetActiveAppInMetadata(0);
       Bootloader_Start();
    }

    if (Bootloader_ValidateBootloadable(1) == CYRET_SUCCESS)
    {
        Bootloader_Exit(Bootloader_EXIT_TO_BTLDB_2); 
    }

    if (Bootloader_ValidateBootloadable(1) == CYRET_BAD_DATA)
    {
        UART_PutString("APP2 Bad");
    }
    if (Bootloader_ValidateBootloadable(0) == CYRET_SUCCESS)
    {
        Bootloader_Exit(Bootloader_EXIT_TO_BTLDB_1); 
    }

    if (Bootloader_ValidateBootloadable(0) == CYRET_BAD_DATA)
    {
        UART_PutString("APP1 Bad");
        Timer_2_Start();
    }    

    for(;;)
    {  
    }
}

Bootloadable Firmware 
For the Bootloadable applications the firmware was made the same. To differentiate between the active applications the flashing LED rate was set for 1s in Application 1 and 2s for Application 2. A compare value in the Timer (System) component was used to configure the flash rate. 

/**
* @file main.c
*
* @version 1.0
*
* @brief Shell example for Cypress Dual Application Bootloadable project                                      
*/

#include <project.h>
#include <stdlib.h>
#include <stdbool.h>

CY_ISR_PROTO(SYS_TMR_HANDLER);
/**
* @brief System timer, flashes LED 2 sec
*/
CY_ISR(SYS_TMR_HANDLER)
{   
     LED_Write(~LED_Read());
    Timer_2_ReadStatusRegister();
    isr_SysTmr_ClearPending();   
}

/**
* @brief Init PSoC
*/
void PSoC_Init() 
{                                                             
    Timer_2_Start();
    isr_SysTmr_StartEx(SYS_TMR_HANDLER);                                                   
}

/**
* @brief Handle main
*/
int main()
{        
    CyGlobalIntEnable;
    PSoC_Init();
    for(;;)
    {                         
    }
}


Bootloadable Firmware Build
Other than selecting Build All Projects from the Build menu in PSoC Creator, no other changes were required. Following a successful build process, several files are generated. For this blog the project was built in Debug with relevant .hex and .cyacd files located in the location \CortexM3\ARM_GCC_541\Debug.

Bootloader Firmware Testing 
To test the Bootloader only the Bootloader application was programmed into the PSoC5 development board. 

Running standalone and without the USB (Micro USB) connected, the serial debug returned the string "APP2 Bad" followed by "APP1 Bad". With no valid application detected the onboard LED was flashed at a fast rate courtesy of system timer.

With the KitProg disconnected and the USB (Micro USB) connected the Bootloader set the onboard LED to ON and started the Cypress Bootloader.

To test programming of the Bootloadable application the Bootloader Host application, from the PSoC Creator Tools menu, was launched. This application provided the interface for updating Application 2; Application 1 was marked as a Golden Application and cannot be updated even if it is not programmed.


Cypress Bootloader Host Application with USB Connection
Cypress Bootloader Host Application with USB Connection

The Bootloader Host application indicated the Active Application in the top right hand corner of the window. Attempting to program the relevant .cyacd file for Application 1 resulted in an error relating to the active application as shown in the capture below. Application 1 was marked as the active application by the Bootloader using the call Bootloader_SetActiveAppInMetadata(0). 

Modifying the code to switch between the active applications should be possible.


PSoC Application Marked Active Message
PSoC Application Marked Active Message

  Attempting to program Application 2 with Application 1 results in a checksum error message as shown below.


Programming PSoC Application 1 onto Application 2 Message
Programming PSoC Application 1 onto Application 2 Message

  While programing Application 2 with the relevant file, App2_2.cyacd is possible and programming is successful, there is no relevance as this is a dual application project with a golden Application 1.

Bootloader with Bootloadable 1 Firmware Testing 
For the following sets of tests the Bootloader and Bootloadable Application 1 was programmed into the PSoC5 development board.

Running standalone and without the USB (Micro USB) connected, the serial debug returned the string "APP2 Bad". With Application 1 returned as valid the application is started. To validate operation of the application, the onboard LED was flashed at a rate of 1 sec ON then OFF.

As with the initial Bootloader test, the KitProg was disconnected and the USB (Micro USB) connected. The Bootloader set the onboard LED to ON and started the Cypress Bootloader.


Again launching the Bootloader Host from the PSoC Creator Tools menu provided the interface for updating Application 2; Application 1 was marked as the Active Application.

Programing Application 2 with the relevant file, App2_2.cyacd, was completed without error.

PSoC Application 2 Programmed Message
PSoC Application 2 Programmed Message

  After cycling the power to the development board, Application 2 was detected as a valid application by the Bootloader and was started. The onboard LED was flashed at a rate of 2 sec ON then OFF.


Project Uses
The proposed implementation in this project may be useful for designs where a minimum operating firmware is required for a product or design. This minimum operating firmware would be considered the Golden application version. A dual application with a Golden application also addresses the issue of application corruption during download, although this event is possible although unlikely.

A further application for a dual application project may be in a commercial product environment. Consider that a commercial product may require end to end device testing which requires a separate firmware implementation to function with a test environment. With modification of the firmware to select applications, a dual application project could allow for execution of either firmware thereby minimising reprogramming.

Some limitations of this project implementation relates to the increased use of memory space and the need to provide specific Bootloadable applications. These applications must occupy the memory locations as defined by the Cypress documentation and project software.

Downloads
The PSoC Creator 4.2 project for the example in this blog was saved as a minimal archive.

USBFS Bootloader with Dual Bootloadable Applications
USBFS Bootloader with Dual Bootloadable Applications

Tuesday, 1 May 2018

PSoC 5 Bootloader USB vs UART I2C Speeds

Summary
This purpose of this blog was to test the download speeds of a PSoC 5 development kit using the KitProg I2C, UART and compare the results against the on-board USB to PSoC interface. 

Test Hardware
A Cypress PSoC development kit CY8CKIT-059 was used with a PSoC Creator project that was configured to test the KitProg SCB I2C and UART components, then secondly a SCB UART connected to an external adaptor and lastly USB interfaced directly to the PSoC 5 with the relevant USB component.


CY8CKIT-059 with External UART Header
CY8CKIT-059 with External UART Header
For UART testing which did not use the Kitprog interface a separate USB to Serial converter from Prolific was utilised. The adaptor was the same type, USB to TTL Serial Cable - Debug / Console Cable for Raspberry Pi from Adafruit as used in a previous blog for similar PSoC 4 tests. The TTL connections to the Prolific adaptor, Black wire was connected to 0V, White to pin P1.6 and Green to pin P1.7 of the Cypress Kit.


Prolific USB to TLL Converter
Prolific USB to TLL Converter
For the Kitprog UART connections in PSoC Creator, P12.7 was used for Tx and P12.6 for Rx. Kitprog I2C connections in Creator used P12.1 for SDA and P12.0 for SCL. 

Test Software
As used in a previous blog, a Creator project related to the DS18B20 was used as the bootloadable component for testing. There were some changes moving between the original PSoC 4 based project to the PSoC 5. These changes resulted in a file size change from 20kb to 28kb.

Where possible, the PSoC Creator PSoC 5 example USBFS project had only minimal changes applied. The PLL Clock was adjusted to achieve the best results for the UART clock when PSoC Creator displayed tolerance warnings. 

Reference Download USB
There were no misgivings that a direct USB interface into the PSoC 5 would result in a fast bootloader time - in fact, the result was almost immediate - for such a small bootloadable file!

UART Download
There is a technical document from Cypress regarding the Kitprog hardware bridge communications speeds for the PSoC5 Development Kit. On page 6 of the Kitprog document is a table showing the programming speed limits for the various interfaces, as shown below.


Kitprog User Guide Table 2-3
Kitprog User Guide Table 2-3
Of interest are the maximum speeds for the I2C and UART facilitated by the USB bridge. In the Cypress community forum there is a thread stating that faster communications speeds are possible, however this is not covered by this blog.

It should be noted that the external Prolfic USB to TTL adaptor hardware is capable of data rates far in excess of the 921600 maximum listed in the Cypress Bootloader Host.

Cypress Windows Bootloader Host
For all the download test performed, the Cypress Bootloader Host was used from within PSoC Creator. The other standalone Windows application known as Cypress UART Bootloader application supports baud rates to 115200 only.


Cypress Bootloader Host
Cypress Bootloader Host
Baud Rate Clocks (SCB)
The change to the PLL clock in the Creator project, as shown below, was required for baud rates above 230400 baud. This clock change was implemented due to the warning raised by PSoC Creator relating to clock accuracy.


PSoC Creator Clock Tolerance Warning
PSoC Creator Clock Tolerance Warning

An change to the clock was instigated under the Clock tab in Creator's Design Wide Resources. The PLL Out Clock was reduced from 48Mhz to 44.3MHz when using the UART with the external Prolific adaptor.


PSoC Creator Change to PLL Out Clock
PSoC Creator Change to PLL Out Clock

I2C Configuration
For the Slave I2C, the data rates were changed from 50 to 1000kbps in the PSoC Creator component.


PSoC Creator I2C Component Configuration
PSoC Creator I2C Component Configuration

A corresponding change was made to the Bootloader Host application to match the data rate.


UART Configuration

The UART was configured in the same manner for tests using Kitprog and the Prolific adaptor.


UART SCB Component Configuration
UART SCB Component Configuration
For the Bootloader component the Tx and Rx buffer were configured for 64 bytes as required.

Test Results
Listed below are the test results for the USB, UART and I2C communications.


Cypress Bootloader Download Times for PSoC5
Cypress Bootloader Download Times for PSoC5
A few items should be noted in the above table. Firstly the USB speed is 'constant'. Appropriately the Cypress Bootloader Host application does not display a baud rate option when the PSoC5 USB port is selected. Secondly the Kitprog UART and I2C interfaces operate to 115200 baud and 100,000 khz as detailed by Cypress.

Graphing the results provides a pertinent visual of how much faster the USB interface, shown in blue, is over Kitprog or a standard UART interfaces. The Kitprog I2C interface does deserves an honourable mention as it closer in download times to the USB compared to UART.


Graphed Cypress Bootloader Download Times for USB, I2C and UART
Graphed Cypress Bootloader Download Times for USB, I2C and UART



Code and Project
The code snippet for the Bootloader application as taken from the Cypress USB PSoC 5 example is listed below.

/*******************************************************************************
* File Name: main.c
*
* Version: 3.0
*
* Description:
*  This example project demonstrates the basic operation of the Bootloader and 
*  Bootloadable components when the communication interface is a USB.
*
********************************************************************************
* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved.
* This software is owned by Cypress Semiconductor Corporation and is protected
* by and subject to worldwide patent and copyright laws and treaties.
* Therefore, you may use this software only as provided in the license agreement
* accompanying the software package from which you obtained this software.
* CYPRESS AND ITS SUPPLIERS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
* WITH REGARD TO THIS SOFTWARE, INCLUDING, BUT NOT LIMITED TO, NONINFRINGEMENT,
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*******************************************************************************/

#include <main.h>


/*******************************************************************************
* Function Name: main
********************************************************************************
*
* Summary:
*  The main function performs the following actions:
*   1. Indicates that the bootloader project is running by turning on the LED.
*   2. Starts the bootloader component and it waits for the application update. 
*      After 10 seconds, the code jumps to the application if it is available. 
*      Otherwise waits forever for application upload.
*
* Parameters:
*  None.
*
* Return:
*  None.
*
*******************************************************************************/
int main()
{
    /* Indicates that the bootloader is running. */
#if (CY_PSOC4)
    RGB_LED_ON_RED;
#else
    TURN_ON_LED4;
#endif /* (CY_PSOC4) */

    /* Enters the bootloader to wait for the application update. */
    Bootloader_Start();

    /* Bootloader_Start() never returns. */
    for (;;)
    {
    }
}


/* [] END OF FILE */
 

Lastly the PSoC 5 project which contains the Bootloader and Bootloadable applications.


Bootloader - Bootloadable Test Application
Bootloader - Bootloadable Test Application


Saturday, 14 April 2018

PSoC 4 Bootloader UDB vs SCB Speeds

Summary
This purpose of this blog was to test and verify, partially for my own curiosity, the download speeds of I2C, UART and UART operating as RS485 for the PSoC 4 using UDB and SCB type components. Operating the SCB UART in RS485 was not possible as an out of box setup, so this test was omitted.

Test Hardware
A Cypress PSoC development kit CY8CKIT-042 was configured to use the on-board I2C, UART or UART (RS485) using UDB and SCB components.

CY8CKIT-042
CY8CKIT-042 - Courtesy Cypress Semiconductor

For UART testing, a separate USB to Serial converter by 
Prolific was utilised. The model from Adafruit for instance was USB to TTL Serial Cable - Debug / Console Cable for Raspberry Pi. For connecting the TTL end of the Prolific cable, the Black wire was connected to 0V, White to pin P0.5 and Green to pin P0.4 of the Cypress Development Kit.


Prolific USB to TLL Converter
Prolific USB to TLL Converter

Similarly a USB to RS485 converter by FTDI was used in conjunction with a LinkSprite RS485 Rev1 adaptor board to connect between the target PC and the Cypress development board. Some hardware modifications were required on the earlier model LinkSprite for use with the Cypress Development board. These changes were related to the Receive and Transmit Enable lines which needed to be driven from the PSoC using the UDB components TX Enable output. The following link LinkSprite RS485.pdf, shows the modifications made to the LinkSprite Rev 1 board.

FTDI USB-RS485-WE-1800-BT
FTDI USB-RS485-WE-1800-BT

LinkSprite (RS485) Fitted to PSoC Development Board
LinkSprite (RS485) Fitted to PSoC Development Board

From the FTDI RS485 adaptor to the LinkSprite only the Data+ and Data- connections were used, which corresponds to the Orange and Yellow wires, as shown in the image above.

Test Software
An application for the DS18B20 OneWire bus was converted into a bootloadable project for testing. Any project could have been used, this was handy at the time. It should be noted that the programming file .CYACD used for testing was less than 20kb.

As mentioned in the blog introduction, both UDB and SCB communications solutions were tested. Where possible the Cypress project and components were left with minimal changes. Clocks with fractional dividers were used to achieve the best tolerance for the communications rates. Note that other methods of deriving the most desirable clock for the given baud rate were not tried - only minimal changes were made to the project.

Some notes on the testing performed.

Reference Download I2C
In most instances, when using a 042 Cypress Development Kit, the Kitprog hardware interface is used to update the target PSoC device from PSoC Creator. The time to perform an update could be determined from PSoC Creator although it would be unlikely that a field solution would use a Kitprog interface for updating the PSoC. I2C was therefore used as the reference for download speeds on this development kit.

Cypress Windows Bootloader Host
For all of the downloads performed, the Cypress Bootloader Host was used from within PSoC Creator. The Cypress UART Bootloader application does not support baud rates above 115200 at the time of writing.


Cypress Bootloader Host
Cypress Bootloader Host
Baud Rate Clocks (SCB)
The clocks shown below were used for UART testing, with the oversampling setting left at the default of 12, for a range from 57,600 to 921600 baud. This was implemented due to the warning raised by PSoC Creator relating to clock accuracy. All rates below 57,600 did not show a warning relating to tolerance.


PSoC Creator Clock Tolerance Warning
PSoC Creator Clock Tolerance Warning


SCB UART 56,700 Clock Input
SCB UART 56,700 Clock Input


SCB UART 115,200 Clock Input
SCB UART 115,200 Clock Input


SCB UART 230,400 Clock Input
SCB UART 230,400 Clock Input
SCB UART 460,800 Clock Input
SCB UART 460,800 Clock Input
SCB UART 921,600 Clock Input
SCB UART 921,600 Clock Input
Baud Rate Clocks (UDB)
The clocks shown below were used for UART testing from 460,800 to 921600 baud. All rates below 460,800 did not show a tolerance warning.


UDB UART 460,800 Clock Input
UDB UART 460,800 Clock Input
UDB UART 921,600 Clock Input
UDB UART 921,600 Clock Input

I2C Configuration
For the I2C (not EZI2C) the data rates were changed from 50 to 1000kbps in the PSoC Creator component.


PSoC Creator I2C Component Bootloader Configuration
PSoC Creator I2C Component Bootloader Configuration
A corresponding change was made to the Bootloader Host application to match the data rate - example capture of the 1000kbps shown below..


PSoC Creator Bootloader Host I2C 1000kbps
PSoC Creator Bootloader Host I2C 1000kbps
UART Configuration
The UART was configured in the same manner for the UDB and SCB components with the exception of the RS485 TX Enable line which is not available on the SCB component for the PSoC4.


UART SCB Component Basic Configuration
UART SCB Component Basic Configuration
UART SCB Component Advanced Configuration
UART SCB Component Advanced Configuration
The oversampling setting was unchanged at 12 and the Tx and Rx buffer were configured for 64 bytes as required for the Bootloader component.


UART UDB Component Configuration
UART UDB Component Configuration
UART UDB Component Advanced Configuration
UART UDB Component Advanced Configuration
For the UDB component the Tx and Rx buffer were configured for 64 bytes as required for the Bootloader component. When required, the hardware TX Enable output was enable in the UDB component.

Test Results
After all the setup detail above, the results recorded from the Cypress Bootloader application with a PSoC 4 are listed in the table below.


Cypress Bootloader Download Times for UDB and SCB Components
Cypress Bootloader Download Times for UDB and SCB Components
The same tests were conducted several times and it should be noted that there was some variation in the results. As a percentage the variation was no more than five percent.

Graphing the recorded results listed above, the shortest time for download is easily visible, the SCB UART. Coming in a close second is the I2C connection seen on most Cypress development kits. The results do show how dedicated hardware on the PSoC 4 performs notably better than Universal Digital Blocks (UDB).


Graphed Cypress Bootloader Download Times for UDB and SCB Components
Graphed Cypress Bootloader Download Times for UDB and SCB Components
Code and Project
The code snippet for the Bootloader application is listed below.

/* ========================================
 *  Shell code for running the bootloader
 * ========================================
*/

#include "project.h"

int main(void)
{
    CyGlobalIntEnable;      /* Enable global interrupts. */   
    Bootloader_Start();     /* Start bootloader, wait forever */

    for(;;)
    {
    }
}

/* [] END OF FILE */ 

Lastly the project itself which contains the Bootloader and Bootloadable applications.


Bootloader - Bootloadable Test Application
Bootloader - Bootloadable Test Application