PSoC 5 Bootloader USB vs UART I2C Speeds

Summary

This purpose of this blog was to test the download speeds of a PSoC 5 development kit using the KitProg I2C, UART and compare the results against the on-board USB to PSoC interface. 

Test Hardware

A Cypress PSoC development kit CY8CKIT-059 was used with a PSoC Creator project that was configured to test the KitProg SCB I2C and UART components, then secondly a SCB UART connected to an external adaptor and lastly USB interfaced directly to the PSoC 5 with the relevant USB component.

CY8CKIT-059 with External UART Header

For UART testing which did not use the Kitprog interface a separate USB to Serial converter from Prolific was utilised. The adaptor was the same type, USB to TTL Serial Cable - Debug / Console Cable for Raspberry Pi from Adafruit as used in a previous blog for similar PSoC 4 tests. The TTL connections to the Prolific adaptor, Black wire was connected to 0V, White to pin P1.6 and Green to pin P1.7 of the Cypress Kit.

Prolific USB to TLL Converter

For the Kitprog UART connections in PSoC Creator, P12.7 was used for Tx and P12.6 for Rx. Kitprog I2C connections in Creator used P12.1 for SDA and P12.0 for SCL. 

Test Software

As used in a previous blog, a Creator project related to the DS18B20 was used as the bootloadable component for testing. There were some changes moving between the original PSoC 4 based project to the PSoC 5. These changes resulted in a file size change from 20kb to 28kb.

Where possible, the PSoC Creator PSoC 5 example USBFS project had only minimal changes applied. The PLL Clock was adjusted to achieve the best results for the UART clock when PSoC Creator displayed tolerance warnings. 

Reference Download USB
There were no misgivings that a direct USB interface into the PSoC 5 would result in a fast bootloader time - in fact, the result was almost immediate - for such a small bootloadable file!

UART Download
There is a technical document from Cypress regarding the Kitprog hardware bridge communications speeds for the PSoC5 Development Kit. On page 6 of the Kitprog document is a table showing the programming speed limits for the various interfaces, as shown below.

Kitprog User Guide Table 2-3

Of interest are the maximum speeds for the I2C and UART facilitated by the USB bridge. In the Cypress community forum there is a thread stating that faster communications speeds are possible, however this is not covered by this blog.

It should be noted that the external Prolfic USB to TTL adaptor hardware is capable of data rates far in excess of the 921600 maximum listed in the Cypress Bootloader Host.

Cypress Windows Bootloader Host
For all the download test performed, the Cypress Bootloader Host was used from within PSoC Creator. The other standalone Windows application known as Cypress UART Bootloader application supports baud rates to 115200 only.

Cypress Bootloader Host

Baud Rate Clocks (SCB)
The change to the PLL clock in the Creator project, as shown below, was required for baud rates above 230400 baud. This clock change was implemented due to the warning raised by PSoC Creator relating to clock accuracy.

PSoC Creator Clock Tolerance Warning

An change to the clock was instigated under the Clock tab in Creator's Design Wide Resources. The PLL Out Clock was reduced from 48Mhz to 44.3MHz when using the UART with the external Prolific adaptor.

PSoC Creator Change to PLL Out Clock

I2C Configuration
For the Slave I2C, the data rates were changed from 50 to 1000kbps in the PSoC Creator component.

PSoC Creator I2C Component Configuration

A corresponding change was made to the Bootloader Host application to match the data rate.

UART Configuration
The UART was configured in the same manner for tests using Kitprog and the Prolific adaptor.

UART SCB Component Configuration

For the Bootloader component the Tx and Rx buffer were configured for 64 bytes as required.

Test Results

Listed below are the test results for the USB, UART and I2C communications.

Cypress Bootloader Download Times for PSoC5

A few items should be noted in the above table. Firstly the USB speed is 'constant'. Appropriately the Cypress Bootloader Host application does not display a baud rate option when the PSoC5 USB port is selected. Secondly the Kitprog UART and I2C interfaces operate to 115200 baud and 100,000 khz as detailed by Cypress.

Graphing the results provides a pertinent visual of how much faster the USB interface, shown in blue, is over Kitprog or a standard UART interfaces. The Kitprog I2C interface does deserves an honourable mention as it closer in download times to the USB compared to UART.

Graphed Cypress Bootloader Download Times for USB, I2C and UART

Code and Project

The code snippet for the Bootloader application as taken from the Cypress USB PSoC 5 example is listed below.

/*******************************************************************************
* File Name: main.c
*
* Version: 3.0
*
* Description:
*  This example project demonstrates the basic operation of the Bootloader and 
*  Bootloadable components when the communication interface is a USB.
*
********************************************************************************
* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved.
* This software is owned by Cypress Semiconductor Corporation and is protected
* by and subject to worldwide patent and copyright laws and treaties.
* Therefore, you may use this software only as provided in the license agreement
* accompanying the software package from which you obtained this software.
* CYPRESS AND ITS SUPPLIERS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
* WITH REGARD TO THIS SOFTWARE, INCLUDING, BUT NOT LIMITED TO, NONINFRINGEMENT,
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*******************************************************************************/

#include <main.h>


/*******************************************************************************
* Function Name: main
********************************************************************************
*
* Summary:
*  The main function performs the following actions:
*   1. Indicates that the bootloader project is running by turning on the LED.
*   2. Starts the bootloader component and it waits for the application update. 
*      After 10 seconds, the code jumps to the application if it is available. 
*      Otherwise waits forever for application upload.
*
* Parameters:
*  None.
*
* Return:
*  None.
*
*******************************************************************************/
int main()
{
    /* Indicates that the bootloader is running. */
#if (CY_PSOC4)
    RGB_LED_ON_RED;
#else
    TURN_ON_LED4;
#endif /* (CY_PSOC4) */

    /* Enters the bootloader to wait for the application update. */
    Bootloader_Start();

    /* Bootloader_Start() never returns. */
    for (;;)
    {
    }
}


/* [] END OF FILE */
 

Lastly the PSoC 5 project which contains the Bootloader and Bootloadable applications.

Bootloader - Bootloadable Test Application

PSoC 4 Bootloader UDB vs SCB Speeds

Summary

This purpose of this blog was to test and verify, partially for my own curiosity, the download speeds of I2C, UART and UART operating as RS485 for the PSoC 4 using UDB and SCB type components. Operating the SCB UART in RS485 was not possible as an out of box setup, so this test was omitted.

Test Hardware

A Cypress PSoC development kit CY8CKIT-042 was configured to use the on-board I2C, UART or UART (RS485) using UDB and SCB components.

CY8CKIT-042 - Courtesy Cypress Semiconductor

For UART testing, a separate USB to Serial converter by Prolific was utilised. The model from Adafruit for instance was USB to TTL Serial Cable - Debug / Console Cable for Raspberry Pi. For connecting the TTL end of the Prolific cable, the Black wire was connected to 0V, White to pin P0.5 and Green to pin P0.4 of the Cypress Development Kit.

Prolific USB to TLL Converter

Similarly a USB to RS485 converter by FTDI was used in conjunction with a LinkSprite RS485 Rev1 adaptor board to connect between the target PC and the Cypress development board. Some hardware modifications were required on the earlier model LinkSprite for use with the Cypress Development board. These changes were related to the Receive and Transmit Enable lines which needed to be driven from the PSoC using the UDB components TX Enable output. The following link LinkSprite RS485.pdf, shows the modifications made to the LinkSprite Rev 1 board.

FTDI USB-RS485-WE-1800-BT

LinkSprite (RS485) Fitted to PSoC Development Board

From the FTDI RS485 adaptor to the LinkSprite only the Data+ and Data- connections were used, which corresponds to the Orange and Yellow wires, as shown in the image above.

Test Software

An application for the DS18B20 OneWire bus was converted into a bootloadable project for testing. Any project could have been used, this was handy at the time. It should be noted that the programming file .CYACD used for testing was less than 20kb.

As mentioned in the blog introduction, both UDB and SCB communications solutions were tested. Where possible the Cypress project and components were left with minimal changes. Clocks with fractional dividers were used to achieve the best tolerance for the communications rates. Note that other methods of deriving the most desirable clock for the given baud rate were not tried - only minimal changes were made to the project.

Some notes on the testing performed.

Reference Download I2C
In most instances, when using a 042 Cypress Development Kit, the Kitprog hardware interface is used to update the target PSoC device from PSoC Creator. The time to perform an update could be determined from PSoC Creator although it would be unlikely that a field solution would use a Kitprog interface for updating the PSoC. I2C was therefore used as the reference for download speeds on this development kit.

Cypress Windows Bootloader Host
For all of the downloads performed, the Cypress Bootloader Host was used from within PSoC Creator. The Cypress UART Bootloader application does not support baud rates above 115200 at the time of writing.

Cypress Bootloader Host

Baud Rate Clocks (SCB)
The clocks shown below were used for UART testing, with the oversampling setting left at the default of 12, for a range from 57,600 to 921600 baud. This was implemented due to the warning raised by PSoC Creator relating to clock accuracy. All rates below 57,600 did not show a warning relating to tolerance.

PSoC Creator Clock Tolerance Warning

SCB UART 56,700 Clock Input

SCB UART 115,200 Clock Input

SCB UART 230,400 Clock Input

SCB UART 460,800 Clock Input

SCB UART 921,600 Clock Input

Baud Rate Clocks (UDB)
The clocks shown below were used for UART testing from 460,800 to 921600 baud. All rates below 460,800 did not show a tolerance warning.

UDB UART 460,800 Clock Input

UDB UART 921,600 Clock Input

I2C Configuration
For the I2C (not EZI2C) the data rates were changed from 50 to 1000kbps in the PSoC Creator component.

PSoC Creator I2C Component Bootloader Configuration

A corresponding change was made to the Bootloader Host application to match the data rate - example capture of the 1000kbps shown below..

PSoC Creator Bootloader Host I2C 1000kbps

UART Configuration
The UART was configured in the same manner for the UDB and SCB components with the exception of the RS485 TX Enable line which is not available on the SCB component for the PSoC4.

UART SCB Component Basic Configuration

UART SCB Component Advanced Configuration

The oversampling setting was unchanged at 12 and the Tx and Rx buffer were configured for 64 bytes as required for the Bootloader component.

UART UDB Component Configuration

UART UDB Component Advanced Configuration

For the UDB component the Tx and Rx buffer were configured for 64 bytes as required for the Bootloader component. When required, the hardware TX Enable output was enable in the UDB component.

Test Results

After all the setup detail above, the results recorded from the Cypress Bootloader application with a PSoC 4 are listed in the table below.

Cypress Bootloader Download Times for UDB and SCB Components

The same tests were conducted several times and it should be noted that there was some variation in the results. As a percentage the variation was no more than five percent.

Graphing the recorded results listed above, the shortest time for download is easily visible, the SCB UART. Coming in a close second is the I2C connection seen on most Cypress development kits. The results do show how dedicated hardware on the PSoC 4 performs notably better than Universal Digital Blocks (UDB).

Graphed Cypress Bootloader Download Times for UDB and SCB Components

Code and Project

The code snippet for the Bootloader application is listed below.

/* ========================================
 *  Shell code for running the bootloader
 * ========================================
*/

#include "project.h"

int main(void)
{
    CyGlobalIntEnable;      /* Enable global interrupts. */   
    Bootloader_Start();     /* Start bootloader, wait forever */

    for(;;)
    {
    }
}

/* [] END OF FILE */ 

Lastly the project itself which contains the Bootloader and Bootloadable applications.

Bootloader - Bootloadable Test Application