Showing posts with label cy8ckit-059. Show all posts
Showing posts with label cy8ckit-059. Show all posts

Monday, 1 June 2020

Mikroe Buck 5 Click with PSoC5 VDAC

Summary
This post examines alternate means for driving the MikroElektronica Buck 5 Click hardware. First, the onboard digital Potentiometer was rewired in a new configuration and second the Potentiometer was replaced with Cypress PSoC.

Buck 5 Click - Courtesy MikroElektronica
Buck 5 Click - Courtesy MikroElektronica

Buck 5 Click with Digital Potentiometer and PSoC5
MikroElektronica's Buck 5 Click (MIKROE-3100) hardware presented itself as a cost-effective and off the shelf unit for testing the MAX17506 DC-DC Converter. The Buck 5 Click was designed primarily for use with other MikroElektronica hardware. The input voltage range of the Maxim buck converter (4.5V to 60 V DC) is not fully utilised on the Buck 5 Click (5V to 30 V DC). In the same manner, the output voltage appears capped at 20 V DC maximum. Even with the voltage limits the output range of the hardware was able to be tweaked. 


Wiring a Cypress CY8CKIT-059 prototyping kit to drive the Buck 5 Click required three connections for the SPI and two for power. The Buck 5 Click schematics indicated the board logic operated with 3.3 V DC however, the board was powered from 5 V DC. The supply range of the MAX5401 digital Potentiometer (pot) was 2.7 V to 5.5 V DC.

To control the digital pot, a PSoC Creator application using an SPI Master component was created


SPIM_WriteTxData(Buck5_Dig_Pot_Val);
while (0u == (SPIM_ReadTxStatus() & SPIM_STS_SPI_DONE)) 
{ }



The subsequent step of increasing the output voltage range of the Buck 5 Click was accomplished although the configuration of feedback resistor network (R8) and digital pot (U2) for the DC-DC converter (MAX17506) needed to switch places. The digital pot operating voltage was the reason for the change. The pot wiper was connected directly into the feedback pin of the MAX17506. Below is a working board with modifications.


Buck 5 Click Modified with Increased Output Range
Buck 5 Click Modified with Increased Output Range



The output voltage range of the modified board was approximately 4V to 18 V DC. The digital pot, with 255 positions, provided output voltage steps of 55 mV.

When applying power to the digital pot, the default setting is the middle position which may not be ideal in all instances. To control the behaviour of the buck regulator on power-up, a connection from the PSoC to the Enable line of the Buck 5 Click was used. A pull-up resistor (R4) was removed from the board to prevent the Buck 5 Click from starting when power was applied

Buck 5 Click with Cypress PSOC5 VADC, No Digital Potentiometer
Other solutions for adjusting the output voltage of a DC-DC converter, through control of the feedback pin, use external PWM or DAC sources.

The Cypress PSoC provides control of DC-DC converters either through PWM (Trim and Margin component) or a DAC (Current or Voltage component). This post used the PSoC VDAC8 component which provided 255 steps. For additional resolution the dithered VDAC component with 4096 steps could be used.

For calculating the output voltage for VDAC solution, Maxim published a notable tutorial deriving the output equation shown below from first principles.

VOUT = VREF(1 + (R1/R2)) + (VREF - VDAC) (R1/R3)                        Eq (1)

For connection of the VDAC to the feedback loop of the DC-DC Converter, one additional resistor (R3) was required.


DC-DC Converter Output Voltage Control Using a DAC
DC-DC Converter Output Voltage Control Using a DAC

A spreadsheet was used to implement Equation (1) which allowed the three unknown resistor values to be manually changed and the output voltage range of the DC-DC converter observed.

DC-DC Converter Vout Spreadsheet Calculations
DC-DC Converter Vout Spreadsheet Calculations

Equation (2) was used to ensure that the maximum current seen by the PSoC (DAC) was less than 25 mA.

i3 = (VREF - VDAC)/R3                       Eq. (2)

Quadrature Encoder
A quadrature encoder (Bourns PEC11R) was added to the design to allow for manual voltage adjustments. The QuadDec component was used to convert the encoder AB lines. The QuadDec returned value was limited to between 0 and 255. The reading from the QuadDec was then used to adjust the output of the VDAC component.


PSoC Creator Top Design
The project required the QuadDec, DAC and OpAmp components as shown below.


PSoC Creator Project Top Design
PSoC Creator Project Top Design


The calculations in Excel used a voltage range from 0.1 V to 4.08 V which was the option selected in the VDAC component.

VDAC Component Settings
VDAC Component Settings

While not essential, an OpAmp follower was added to the design.

OpAmp Component Settings
OpAmp Component Settings

To maintain 255 positions the QuadDec component was changed from the default 8 bit to 16 bits.

QuadDec Component Settings
QuadDec Component Settings

The remaining signals that are shown on the PSoC Creator project page (Top Design) were related to the DC-DC converter (PSU_Enable) and the on-board switch (Switch1). Voltage ramps were generated in code on start-up then Switch1 was pressed.

To facilitate testing of the encoder, a UART component was added to the project.

PSoC Creator Pin Mapping
Pin mapping for the design is shown below.



PSoC Project Pin Mapping
PSoC Project Pin Mapping


PSoC Creator Code
Listed below is an extract of some quick and grubby code used for testing the Mikroe with the PSoC Creator prototyping board.



/**
* @brief Main init and update VDAC based on quadrature encoder value
*/
int main()
{
  uint16_6 Encoder_Count, Encoder_Count_last = 0;
CyGlobalIntEnable();
QuadDec_Start();
UART_Start();
Opamp_Start();
VDAC_Start();
CyDelay(2000); /* Time to stabalise */
PSU_Enable_Write(true); /* Switch DC DC On */
pulse_on_switch1();
for(;;)
{
Encoder_Count = QuadDec_GetCounter();
if (Encoder_Count != Encoder_Count_Last)
{
if ((Encoder_Count <= MAX_ENC) && (Encoder_Count >= MIN_ENC))
{
write_to_uart(Encoder_Count);
VDAC_SetValue(Encoder_Count);
}
else if (Encoder_Count > MAX_ENC)
{
Encoder_Count = MAX_ENC;
QuadDec_SetCounter(MAX_ENC);
}
else if (Encoder_Count < MIN_ENC)
{
Encoder_Count = MIN_ENC;
QuadDec_SetCounter(MIN_ENC);
}
Encoder_Count_Last = Encoder_Count;
}
}
}

The functionality of the test code was to read the Quadrature Decoder, ensures the value read was within the range, then write the value to the VDAC.


Hardware Setup
Shown in the image below is the hardware setup which consisted of the Buck 5 Click, PSoC board and the rotary encoder.



Buck 5 Click with Increased Output and PSoC VDAC
Buck 5 Click with Increased Output and PSoC VDAC

Output Voltage Range and Regulation
The calculated output voltage range was for 1.62 V to 20.33 V DC and the measured range was 2.39 V to 20.42 V DC.

Rudimentary load tests were conducted with a resistive load driven by the Buck 5 Click. Tests indicated a 0.25 % voltage regulation with low loads (1W) and better than 0.1 % with higher loads (65 W). The DC-DC converter used in the Buck 5 Click (MAX17506) has a capability of 5 A. The full load current was not load tested.

Output Voltage Adjustment using PSoC
To change the output voltage of the DC-DC converter without the encoder, the value written to the VDAC was controlled in software. When the switch located on the Cypress CY8CKIT-059 prototyping kit was pressed on power-up, the code generated several pulse types.

Buck 5 Click Output Voltage Waveform from PSoC VDAC
Buck 5 Click Output Voltage Waveform driven from PSoC VDAC

The capture above shows the Buck 5 Click output voltage ramp up and down with a 220 R resistive load.

Final Thoughts
The MikroElektronica Buck 5 Click was a reliable hardware module which allowed a Cypress PSoC to be interfaced for testing. Using a DAC to adjust the output voltage provided an alternative method to the on-board Potentiometer. The option to use PWM control for voltage adjustment was not reviewed in this post although this method should be considered as another solution.


Downloads
PSoC Creator 4.3 Power Supply Project (PSU) Project.

PSoC Creator 4.3 PSU Project
PSoC Creator 4.3 PSU Project

Tuesday, 1 May 2018

PSoC 5 Bootloader USB vs UART I2C Speeds

Summary
This purpose of this blog was to test the download speeds of a PSoC 5 development kit using the KitProg I2C, UART and compare the results against the on-board USB to PSoC interface. 

Test Hardware
A Cypress PSoC development kit CY8CKIT-059 was used with a PSoC Creator project that was configured to test the KitProg SCB I2C and UART components, then secondly a SCB UART connected to an external adaptor and lastly USB interfaced directly to the PSoC 5 with the relevant USB component.


CY8CKIT-059 with External UART Header
CY8CKIT-059 with External UART Header
For UART testing which did not use the Kitprog interface a separate USB to Serial converter from Prolific was utilised. The adaptor was the same type, USB to TTL Serial Cable - Debug / Console Cable for Raspberry Pi from Adafruit as used in a previous blog for similar PSoC 4 tests. The TTL connections to the Prolific adaptor, Black wire was connected to 0V, White to pin P1.6 and Green to pin P1.7 of the Cypress Kit.


Prolific USB to TLL Converter
Prolific USB to TLL Converter
For the Kitprog UART connections in PSoC Creator, P12.7 was used for Tx and P12.6 for Rx. Kitprog I2C connections in Creator used P12.1 for SDA and P12.0 for SCL. 

Test Software
As used in a previous blog, a Creator project related to the DS18B20 was used as the bootloadable component for testing. There were some changes moving between the original PSoC 4 based project to the PSoC 5. These changes resulted in a file size change from 20kb to 28kb.

Where possible, the PSoC Creator PSoC 5 example USBFS project had only minimal changes applied. The PLL Clock was adjusted to achieve the best results for the UART clock when PSoC Creator displayed tolerance warnings. 

Reference Download USB
There were no misgivings that a direct USB interface into the PSoC 5 would result in a fast bootloader time - in fact, the result was almost immediate - for such a small bootloadable file!

UART Download
There is a technical document from Cypress regarding the Kitprog hardware bridge communications speeds for the PSoC5 Development Kit. On page 6 of the Kitprog document is a table showing the programming speed limits for the various interfaces, as shown below.


Kitprog User Guide Table 2-3
Kitprog User Guide Table 2-3
Of interest are the maximum speeds for the I2C and UART facilitated by the USB bridge. In the Cypress community forum there is a thread stating that faster communications speeds are possible, however this is not covered by this blog.

It should be noted that the external Prolfic USB to TTL adaptor hardware is capable of data rates far in excess of the 921600 maximum listed in the Cypress Bootloader Host.

Cypress Windows Bootloader Host
For all the download test performed, the Cypress Bootloader Host was used from within PSoC Creator. The other standalone Windows application known as Cypress UART Bootloader application supports baud rates to 115200 only.


Cypress Bootloader Host
Cypress Bootloader Host
Baud Rate Clocks (SCB)
The change to the PLL clock in the Creator project, as shown below, was required for baud rates above 230400 baud. This clock change was implemented due to the warning raised by PSoC Creator relating to clock accuracy.


PSoC Creator Clock Tolerance Warning
PSoC Creator Clock Tolerance Warning

An change to the clock was instigated under the Clock tab in Creator's Design Wide Resources. The PLL Out Clock was reduced from 48Mhz to 44.3MHz when using the UART with the external Prolific adaptor.


PSoC Creator Change to PLL Out Clock
PSoC Creator Change to PLL Out Clock

I2C Configuration
For the Slave I2C, the data rates were changed from 50 to 1000kbps in the PSoC Creator component.


PSoC Creator I2C Component Configuration
PSoC Creator I2C Component Configuration

A corresponding change was made to the Bootloader Host application to match the data rate.


UART Configuration

The UART was configured in the same manner for tests using Kitprog and the Prolific adaptor.


UART SCB Component Configuration
UART SCB Component Configuration
For the Bootloader component the Tx and Rx buffer were configured for 64 bytes as required.

Test Results
Listed below are the test results for the USB, UART and I2C communications.


Cypress Bootloader Download Times for PSoC5
Cypress Bootloader Download Times for PSoC5
A few items should be noted in the above table. Firstly the USB speed is 'constant'. Appropriately the Cypress Bootloader Host application does not display a baud rate option when the PSoC5 USB port is selected. Secondly the Kitprog UART and I2C interfaces operate to 115200 baud and 100,000 khz as detailed by Cypress.

Graphing the results provides a pertinent visual of how much faster the USB interface, shown in blue, is over Kitprog or a standard UART interfaces. The Kitprog I2C interface does deserves an honourable mention as it closer in download times to the USB compared to UART.


Graphed Cypress Bootloader Download Times for USB, I2C and UART
Graphed Cypress Bootloader Download Times for USB, I2C and UART



Code and Project
The code snippet for the Bootloader application as taken from the Cypress USB PSoC 5 example is listed below.

/*******************************************************************************
* File Name: main.c
*
* Version: 3.0
*
* Description:
*  This example project demonstrates the basic operation of the Bootloader and 
*  Bootloadable components when the communication interface is a USB.
*
********************************************************************************
* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved.
* This software is owned by Cypress Semiconductor Corporation and is protected
* by and subject to worldwide patent and copyright laws and treaties.
* Therefore, you may use this software only as provided in the license agreement
* accompanying the software package from which you obtained this software.
* CYPRESS AND ITS SUPPLIERS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
* WITH REGARD TO THIS SOFTWARE, INCLUDING, BUT NOT LIMITED TO, NONINFRINGEMENT,
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*******************************************************************************/

#include <main.h>


/*******************************************************************************
* Function Name: main
********************************************************************************
*
* Summary:
*  The main function performs the following actions:
*   1. Indicates that the bootloader project is running by turning on the LED.
*   2. Starts the bootloader component and it waits for the application update. 
*      After 10 seconds, the code jumps to the application if it is available. 
*      Otherwise waits forever for application upload.
*
* Parameters:
*  None.
*
* Return:
*  None.
*
*******************************************************************************/
int main()
{
    /* Indicates that the bootloader is running. */
#if (CY_PSOC4)
    RGB_LED_ON_RED;
#else
    TURN_ON_LED4;
#endif /* (CY_PSOC4) */

    /* Enters the bootloader to wait for the application update. */
    Bootloader_Start();

    /* Bootloader_Start() never returns. */
    for (;;)
    {
    }
}


/* [] END OF FILE */
 

Lastly the PSoC 5 project which contains the Bootloader and Bootloadable applications.


Bootloader - Bootloadable Test Application
Bootloader - Bootloadable Test Application