Circuit Board Return Path Via Placement Options

Introduction
This blog discusses a few options that new circuit board designers may use for return path vias as a result of signal traces changing circuit board layers through using vias.
 
Further Literature
It is highly recommended that existing content from industry figures such as Eric Bogatin or Rick Hartley are reviewed. Related circuit board information is available from YouTuber channels such as Robert Feranec or Phils Lab to mention a few.

PCB Routing Example
For circuit board designs that feature microcontrollers, microprocessors, FPGA or similar devices with high pin count or spacing density the existing connections to power rails through vias can serve as return paths. In the image below, taken from the Altium Mini-PC board, the green highlighted vias indicate the several 0V (GND) power connections that may function as return paths for the DDR memory address, data, clock and control signals.

Altium Mini-PC Board Highlighted GND (0V) Vias (Courtesy Altium)

 
Reducing Return Path Distance
The capture below is a further extract from the Mini-PC demonstration board showing a distance measurement between a return via and a differential DDR clock pair.

A Texas Instruments Application Note, High-Speed Interface Layout Guidelines, 2023 states that the signal to return via distance should be a maximum distance of 5 mm (200 mil) although that value could be considered design dependent. For the Mini-PC demonstration board, the distance between the return via and differential pair is small, some 2.1 mm.

Altium Mini-PC Board Differential Via Pair (Courtesy Altium)

Consider a situation where the return path distances needed to be reduced. On the Mini-PC board, a smaller distance could be achieved following a circuit board review. Traces on the layers could be moved to make room for a via closer to the differential via pair. The capture below shows one possible change with a reduction to 1.4 mm.

Altium Mini-PC Board with Closer Return Path Via (Courtesy Altium)

Board Space Limitations
A more common limitation when adding or altering return path vias could be related to circuit board space. In the example below, the traces in the red colour identify a differential pair. There is no return path via in close proximity. The while highlighted rectangles represent pads on the other side of the circuit board.

Differential Pair with No Return Path Via on a Double Sided Circuit Board

The reason for no return path via in the area is two-fold. On the opposite side of the circuit board is a surface mount component with large pads making return via placement difficult. The second limitation is due to the PCB rules. The smallest via hole size is configured for 0.3 mm.

The limitation created by the component on the opposite side can be overcome using a number of solutions. Using the existing circuit board via the size of 0.3/0.5 mm (via hole size/via diameter) three vias could be placed onto the circuit board as shown below. This solution yields a differential pair to return path via distance of 2.3 mm.

Differential Pair with Three Return Path Vias on a Double Sided Circuit Board

Differential Pair with Three Return Path Vias on Other Side of Circuit Board

Another solution to consider is changing the board design rules. The circuit board clearance rule could be reduced from 0.2 mm to 0.15 mm since the smaller clearance is supported by many fabrication houses. 

Paired with the board clearance change, the via hole size could be reduced. For instance, a via of hole size and diameter 0.254/0.444 mm could be selected. In regards to capabilities, circuit board fabrication houses can manufacture smaller via hole/diameter measurement of 0.15/0.28 mm (drilled). Applying the two changes mentioned in this section, a via can then be placed less than 1 mm from the differential pair.

Differential Pair with Single Smaller Return Path Via on a Double Sided Circuit Board

No Space or Other Limitations
For some board designs, it may be impractical to place a via close to a signal that requires a return path. Should board space and routing permit, via stitching throughout the board or a via shielding around the board or relevant section of the circuit may be alternative solutions.

Example of Via Stitching on a Circuit Board

Example of Via Shielding on a Circuit Board

Summary
Even though the placement of return path vias may be a semi-automated process with some software design tools, the lack of circuit board space to position vias in optimum locations still vexes novice and experienced board designers alike. This blog puts that other solutions may be found by reviewing the nominated fabrication house’s manufacturing capabilities and the minimum manufacturing circuit board requirements.

Altium Return Path Example Project

Summary
This blog provides an example Altium Designer (Altium) circuit board project which makes use of the ‘Return Path’ rule.

Altium reference material, such as Video content and documentation for configuring the 'Return Path' rule should also be reviewed when considering this feature.

Example
The Altium project for the Altera Cyclone II EP2C35F67C8 DB31.07 Daughter Board ‘DB31’ was used for the blog example. 

Altera Cyclone II EP2C35F67C8 DB31.07 Daughter Board by Altium

A single Printed Circuit Board (PCB) signal layer was used with a reference power plane to illustrate return paths.

PCB Layer Stackup
To achieve the desired board trace impedance, a PCB designer may liaise with a PCB fabrication company to define the layer stack, dielectrics, trace widths and for differential pairs the trace spacing.

As an example, the capture below shows typical information provided by a PCB fabrication company. The PCB was configured for impedance controlled differential pairs on external signal layers and single-ended internal layers.

Example PCB Manufacturer Trace Width Information

The types of material used for the PCB core and pre-preg depends on the capabilities of the PCB fabrication company and budget constraints.

Example PCB Manufacturer Layer Stackup

For the blog example using the DB31 project, the existing layer stack was retained. An arbitrary impedance of 55 R was selected for layer Mid-3 traces which was referenced to a single layer, Ground-5.

Example Project DB31 Layer Stackup and Controlled Impedance

Return Path Rule
As detailed in Altium documentation, the return path must be a fill, region or polygon which is unbroken. After configuring the impedance profile, a new ‘Return Path Rule’ was configured for layer Mid-3.

Altium Return Path Rule No Exclusions

The ‘Exclude Copper Vias’ checkbox was selected to ignore violations under the Altera FPGA as a result of vias. 

Altium Return Path Rule with Exclusions

Design Rule Check (DRC)
After performing a DRC on the original DB31 PCB, several violations required resolution.

DB31 Project PCB Net Antennae

Testing Return Path Violations
With the return path for Mid-2 signals being Ground-5, a cutout was inserted into the ground polygon at a location which resulted in a return path violation.

DB31 Project Cutout in Return Path Reference Plane

DB31 Project Signal Traces

After running a DRC, violations for Return Paths were shown for Mid-2.

DB31 Return Path Violations

Return Path Tolerances
Some factors not detailed in the Altium documentation are the tolerances of the 'Return Path' rule. Tolerances in this case refer to the amount of return path copper which can be removed from beneath the signal trace before a violation is raised by Altium Designer.

For the image shown below a cutout was placed in the return plane, Ground-5, which ran in parallel with the signal trace. This resulted in a violation.

Altium Return Path Violation Parallel Ground Cutout

In the capture below the edge of a rectangular cutout was placed in the return plane, Ground-5, which intersected with the signal trace.

Altium Return Path Violation Tolerance Ground Cutout

A return path violation was raised when the cutout encroached under half of the mid layer track. 

Altium Return Path Violation Tolerance Rectangular Cutout Measurement

Next, a circular cutout was placed in the return plane which resulted in a violation at the position shown in the capture below.

Altium Return Path Violation Tolerance Circular Cutout Measurement

Final Thoughts
For circuit board designs containing features such as DDR memory, high-frequency differential pairs or high-speed inter-chip signals, utilising the 'return path' rule automates the previous manual checking required for return paths.

However, as with any tool, there are tolerances and limitations which would ideally be detailed by the manufacturer. The effects of polygon cutouts, the result of signal trace to return path coverage and details for return paths with coplanar impedance control are some trappings which may of interest to the PCB designer.

Acknowledgements
Thanks to Altium for the DB31 project which was used to illustrate the return path rule in this blog.

Downloads
The updated DB31 project used in the blog.

DB31 Example Project