Circuit Board Return Path Via Placement Options

Introduction
This blog discusses a few options that new circuit board designers may use for return path vias as a result of signal traces changing circuit board layers through using vias.
 
Further Literature
It is highly recommended that existing content from industry figures such as Eric Bogatin or Rick Hartley are reviewed. Related circuit board information is available from YouTuber channels such as Robert Feranec or Phils Lab to mention a few.

PCB Routing Example
For circuit board designs that feature microcontrollers, microprocessors, FPGA or similar devices with high pin count or spacing density the existing connections to power rails through vias can serve as return paths. In the image below, taken from the Altium Mini-PC board, the green highlighted vias indicate the several 0V (GND) power connections that may function as return paths for the DDR memory address, data, clock and control signals.

Altium Mini-PC Board Highlighted GND (0V) Vias (Courtesy Altium)

 
Reducing Return Path Distance
The capture below is a further extract from the Mini-PC demonstration board showing a distance measurement between a return via and a differential DDR clock pair.

A Texas Instruments Application Note, High-Speed Interface Layout Guidelines, 2023 states that the signal to return via distance should be a maximum distance of 5 mm (200 mil) although that value could be considered design dependent. For the Mini-PC demonstration board, the distance between the return via and differential pair is small, some 2.1 mm.

Altium Mini-PC Board Differential Via Pair (Courtesy Altium)

Consider a situation where the return path distances needed to be reduced. On the Mini-PC board, a smaller distance could be achieved following a circuit board review. Traces on the layers could be moved to make room for a via closer to the differential via pair. The capture below shows one possible change with a reduction to 1.4 mm.

Altium Mini-PC Board with Closer Return Path Via (Courtesy Altium)

Board Space Limitations
A more common limitation when adding or altering return path vias could be related to circuit board space. In the example below, the traces in the red colour identify a differential pair. There is no return path via in close proximity. The while highlighted rectangles represent pads on the other side of the circuit board.

Differential Pair with No Return Path Via on a Double Sided Circuit Board

The reason for no return path via in the area is two-fold. On the opposite side of the circuit board is a surface mount component with large pads making return via placement difficult. The second limitation is due to the PCB rules. The smallest via hole size is configured for 0.3 mm.

The limitation created by the component on the opposite side can be overcome using a number of solutions. Using the existing circuit board via the size of 0.3/0.5 mm (via hole size/via diameter) three vias could be placed onto the circuit board as shown below. This solution yields a differential pair to return path via distance of 2.3 mm.

Differential Pair with Three Return Path Vias on a Double Sided Circuit Board

Differential Pair with Three Return Path Vias on Other Side of Circuit Board

Another solution to consider is changing the board design rules. The circuit board clearance rule could be reduced from 0.2 mm to 0.15 mm since the smaller clearance is supported by many fabrication houses. 

Paired with the board clearance change, the via hole size could be reduced. For instance, a via of hole size and diameter 0.254/0.444 mm could be selected. In regards to capabilities, circuit board fabrication houses can manufacture smaller via hole/diameter measurement of 0.15/0.28 mm (drilled). Applying the two changes mentioned in this section, a via can then be placed less than 1 mm from the differential pair.

Differential Pair with Single Smaller Return Path Via on a Double Sided Circuit Board

No Space or Other Limitations
For some board designs, it may be impractical to place a via close to a signal that requires a return path. Should board space and routing permit, via stitching throughout the board or a via shielding around the board or relevant section of the circuit may be alternative solutions.

Example of Via Stitching on a Circuit Board

Example of Via Shielding on a Circuit Board

Summary
Even though the placement of return path vias may be a semi-automated process with some software design tools, the lack of circuit board space to position vias in optimum locations still vexes novice and experienced board designers alike. This blog puts that other solutions may be found by reviewing the nominated fabrication house’s manufacturing capabilities and the minimum manufacturing circuit board requirements.

PCB vias solder mask tenting

Summary

This blog highlights some of the implications for PCB 'board' loaders during the reflow or wave soldering process when Printed Circuit Board (PCB) designers choose not to tent solder side vias.

PCB Manufacturer Tenting Limitations
With the advent of higher density devices such as microcontrollers with configurable logic, Field Programmable Gate Arrays (FPGA), System On Module (SOM), System On Chip (SOC) and high power FET drivers becoming more prevalent in commercial equipment and hobbyist designs, there comes a requirement to manage exposed pads and vias beneath these devices. 

In some instances high density components may have an exposed pad that require a connection utilising vias for a variety of reasons. The exposed pad may serve as electrical connection, such as an input power supply, output in the case of a switch mode regulator, the pad may be used for PCB mounting by providing bonding strength (due to the ever decreasing component footprint) or for heatsinking, by acting as a thermal pad such is the case for high power FET drivers.

In the image below are a few examples of different sized vias which have been used for different reasons on the same PCB.

Tented and Untented Vias

Identified in the red box are vias which are used for standard TTL signal connections. The via hole size is 0.3mm. Vias with this hole size are commonly tented during the PCB manufacturing process using solder resist, unless they have been earmarked for alternative purposes such as test points, probing, programming or other similar purposes.

Shown in the light blue box are larger vias with a 0.7mm hole which are used for connections to the PCB internal power planes. Vias of this size are tented where possible unless there is a good reason not to do so or the PCB manufacturer is unable to mask to this via size. Reasons for not tenting may include thermal connections to exposed pads or a need to increase the current handling capacity of the via. Both of these reasons may require solder or a 'plug' to fill the via.

The purple box shows a cluster of untented vias with a 0.5mm hole. These vias reside below a microcontroller featuring an exposed pad. The vias on both sides of the board are not tented although these vias are usually tented on the solder (non-component) side of the PCB.

Lastly shown in the yellow box is an array of vias with a 0.381mm hole. The grouped formation of vias is commonly termed 'stitching' in software packages such as Altium Designer. For this design the top and bottom copper layer represent the ground plane which are stitched together using multiple vias. Vias of this size and smaller are usually always tented.

For the example board shown, almost all of the vias are listed as tented in the PCB file and the Gerber files. Clearly not all the vias appear to be tented in a thick solder mask. The reason for the discrepancy can lie with the capability of the PCB manufacturer. Not all PCB manufacturers detail their limits for tenting vias with solder mask or are able to open the latest PCB files from software packages such as Altium Designer (a good reason why Gerbers are used in the industry). This issue can be remedied to some degree by supplying the Gerber files to the manufacturer, in the format requested, and then asking to verify the machine Gerber files that the manufacturer intend on using in their PCB production equipment.

PCB designers should be mindful however that even the final Gerber files supplied by the PCB manufacturer may not always be what is actually produced. For example, mutlilayer boards with power planes to the edge of the board will have, in general, a 'pullback' rule applied to that layer even if the PCB does not have a pullback rule. To prevent these rules from being applied by the PCB manufacturer comments or notations should be explicitly noted on the PCB file or Gerber file as 'no pullback on this layer'. Somewhat off topic although this concept also applies indirectly to vias and solder mask.

With regards to the maximum size of via which can be covered with solder mask, for a standard manufacturer a 0.8mm hole may be too large where for the more experienced or better tooled manufacturer, a 1.2mm hole may be considered the upper limit. Asking the manufacturer will at least provide an idea of their manufacturing capability. This information can then be included in the PCB design file for the PCB manufacturer.

Via Placement and Tenting Issues
A single untented via rarely causes placement or issues for the PCB loader. The word rarely is used with caution however because a single, poorly placed via, without tenting can cause issues when located too close to another surface mount component, to the pad of a PCB mount metalised connector or the under the metal body of a mechanical component such as a HDMI connector.

The image below shows vias with an equidistant spacing of 1.1mm connected to a component with an exposed pad on the opposite side of the PCB. A via spacing down to 0.5mm should usually not cause a problem for the PCB loader whether the soldering process is reflow, as shown below, or solder wave.

Via Spacing

Shown in the subsequent image is a higher density via placement with a spacing of 0.8mm. Due to the increased number of untended vias and possibly solder paste, the solder readily flows from the top side of the board to the bottom during the reflow process.

Higher Density Via Spacing

Although the protruding solder could easily be removed as part of the post manufacturing process, this additional work can increase the final PCB cost and is best avoided during PCB design by tenting the vias. It should also be noted that the solder protruding from the vias may not be excess solder but instead solder that should be between the exposed pad of the component and the copper pad of the PCB.

No Via Tenting
Where vias are used for other purposes, such as ground planes or heatsinking, the PCB designer has the option to leave the via with no tenting. During the PCB population process solder may fill the vias, although using solder to fill vias in this manner is not a guaranteed process. The image below shows the via arrangement under a high current switch where not all of the vias have been filled with solder.

Staggered Via Layout Connected to Polygon

The subsequent image shows the component side of the board without the physical component fitted.

Staggered Via Layout Component Side

Via Tenting
Although this blog focuses on vias without tenting, it should be noted and sighted in the image below, that even vias with a 1mm hole can be tented with solder mask by a sufficiently qualified PCB manufacturer.

Tented Vias Connected to Polygon

Design Suggestions
Knowing the limitations of the PCB manufacturer and the PCB loaders soldering process would allow ideal selections to be made during the PCB design process.

This comment is idealistic, not realistic. 

More often than not people utilise online PCB manufacturers which do not fully disclose the capability of their PCB manufacturing equipment. Additionally the PCB manufacturer's website may be a PCB broker that farms large groups of common layer boards to the most suitable PCB manufacturer at that time.

With this in mind, the suggestions below for tenting and spacing, of through PCB vias, are for a typical PCB manufacturer and largely depend of the via size and use.

Max via hole size for tenting: 1.2mm
Min via to via land separation for untented vias: 0.3mm
Min via to via land separation for tented vias: 0.15mm

Tented Vias Connected on Multiple Polygons