Paralleling Outputs of High Side MOSFET Drivers

Introduction
This blog measures the voltage and timing differences during simultaneous control of dual output high-side electronic drivers.

Parallel Dual High-Side Driver Test PCB

Test Device
The electronic component discussed in this blog is the IPS2050H. This device is manufactured by ST Micro. The device is a dual output high-side driver with an operating voltage of DC 8 – 60 V with a current capability of either 2.4 A or 5.6 A.

This ST driver was originally considered for the Interruption Tester project which is detailed in another series of posts. Paralleling the outputs of the IPS2050H for a higher current remained a matter of interest however several characteristics of these devices are not listed in the datasheet. Information such as the difference between channel ON/OFF control voltages or switching times was seen as beneficial.

Paralleling Outputs
Literature on the subject of balancing currents when paralleling discrete MOSFETs is widely available. One such paper, “Paralleling of Power MOSFETs for HigherPower Output”, by James B. Forsythe of International Rectifier, provides a well-documented explanation of effects and techniques to normalise current sharing between MOSFET devices. In this post, some of the points listed in the International Rectifier paper were discussed and applied to the IPS2050H.

For further reading, Texas Instruments has a similar document "High Side Switches Paralleling Channels"

In a document with similar content, Infineon published an application note showing realistic gate voltage for high current applications "Paralleling MOSFETs in high-current LV drive applications"

Discussion
For those readers looking for an immediate answer to paralleling outputs of high-side drivers with multiple outputs, it is possible however the operation depends on the requirements of the load and driver.

The International Rectifier paper for MOSFETs was used as a guideline to review some aspects of the IPS2050H. Items from Section IV (c) Summary of Recommendations for Balancing Parallel MOSFET Currents were applied where possible.

Manufacturing of the IPS2050H would likely be performed on a single silicon wafer however there is commonly variation in characteristics across the wafer. Screening and parameter matching for the IPS2050H are not practical however, measurements were performed to determine differences between the devices two channels.

Parameter differences between channels were noted for Vin (ON) and (OFF).

IPS2050H Measured ON-OFF Voltages

The delays between input and output switching were measured at room  temperature, approximately 1.96 us for both channels.

IPS2050H Input to Output Switching Delay (No Load)

The measurement for the switching delay was performed based on the
50 % input voltage and 10 % output voltage for the propagation delay as shown in Figure 3 of the IPS2050H datasheet.

Figure 3 Timing from IPS2050 Datasheet (Courtesy ST Micro)

When switching the input of both channels ON simultaneously, without a load connected to either, the turn ON delay between channels was approximately 400 ns.

IPS2050H Turn-ON Delay between Outputs

Next, a load consisting of a 10 R wire wound resistor was added to each channel. The turn-ON delay with the resistor was 17 us for one channel and 18 us for the other. The turn-OFF delay with the wire wound resistor was slightly over 7 us for both channels.

IPS2050H Channel 1 Turn-ON Delay with Wire Wound Resistor

IPS2050H Channel 2 Turn-ON Delay with Wire Wound Resistor

The output turn-ON delay between channel 1 and 2 with separate wire wound resistors was slightly over 25 us for both channels.

IPS2050H Channel 1 to 2 Output Turn-ON Delay with Wire Wound Resistors

The output turn-OFF delay between channel 1 and 2 with separate wire wound resistors was again slightly over 7 us for both channels.

IPS2050H Channel 1 to 2 Output Turn-OFF Delay with Wire Wound Resistors

A capacitive load of 6800 uf was driven with various output configurations. For the first test, the two outputs were connected in parallel and wired to the capacitor. The charging waveform is shown below.

IPS2050H Parallel Channel 1 to 2 Capacitor Charging

For the subsequent test, the two outputs each had a 3.3 R current sharing resistor fitted before terminating at the capacitor. As expected the capacitor charge time constant increased because of the introduced resistance.

IPS2050H Parallel Channel 1 to 2 Capacitor Charging through 3.3 R Resistors

In the last configuration, two Schottky diodes were fitted to replace the resistors on each output before connecting to the capacitor.

IPS2050H Parallel Channel 1 to 2 Capacitor Charging through Schottky Diodes

The time to charge the capacitor with Schottky diodes was approximately the same as the directly connected paralleled outputs. Note the lower voltage across the capacitor with the diodes due to forward voltage losses.

Each channel of the IPS2050H driver was individually loaded to 1.5 A and the voltage across separate wire wound resistors was measured with both inputs of the device ON. The output voltage at channel 1 measured 15.051 V and channel 2 measured 15.089 V.

The IPS2050H inputs were driven using a square wave with a 90 % duty cycle. The output voltage at channel 1 measured 14.968 V and channel 2 measured 15.015 V.

Driving IPS2050H Channel 1 and 2 with a Square Wave

PCB Traces
As stated in the paper by International Rectifier, the addition of series resistance would not be required for a design with MOSFETs. The traces on the test PCB outputs were duplicated as shown in the image below.

Highlighted Output Polygon Traces on Top Layer of Test PCB

 

Common source inductance was not reviewed in this post. Since the MOSFET gates are not accessible, drive modifications were not possible. The decoupling resistance (gate resistor) would likely be part of the control circuit block in the IPS2050H, as shown in the capture below, therefore this was also not investigated.

IPS2050H Functional Block Datasheet (Courtesy ST Micro)

Final Thoughts
Measurements performed on the IPS2050H indicated there are minor difference in turn ON/OFF threshold voltages and switching delays. These timing differences may result in one channel of the IPS2050H momentarily handling most of the switching energy at on turn ON and then at turn OFF. This time difference was measured in microseconds for the loads tested, which may be acceptable time for some designs but a hindrance for other designs where high instantaneous currents are required.

For a more comprehensive review, current measurements from each of the parallel outputs in a target circuit would provide clarity on the demand placed on each driver output. Temperature measurements could also prove beneficial to ensure that the device’s maximum operating specifications were not exceeded.

Voltage Interruption Tester for IEC 61496-1 Part 5

Introduction
This blog continues from part 4 and finalised the supply voltage interruption tester (unit) post. 

Covered in this blog is an interruption test applied to a PSoC development board. The test setup consisted of a Rigol DP832, the Interruption tester prototype and the PSoC development board part CY8CKIT-042.

Interruption Test Setup Using PSoC Development Board

This post also provides the source and Gerber files for the interruption tester project.

Practical Interruption Test

Disclaimer - The interruption test performed on the Cypress PSoC development board was performed for the sole purpose of measurement and testing only. The PSoC development board does not claim conformance with the test conducted.

Only interruption test 1 was performed because the operating voltage of the development board was stated as DC 5 – 12 V and the minimum operating voltage for the interruption tester output drivers is DC 8 V. Test 2 and 3 require half the supply voltage which was not practical.
For the program operating on the PSoC board, two outputs of a PWM block were used to separately toggle the onboard bi-colour LED.

When interruption test 1 was enabled, the 3.3 V supply was interrupted which resulted in the processor resetting. This is evident by the irregular operation of the bi-colour LED.

To resolve the issue caused by the dips in the supply rail, a 100 uF electrolytic capacitor was connected across the development board supply.

The two images below show a capture of the 3.3 V supply before and after the 100 uF capacitor was added to the development board.

Capture of Supply Rail During Interruption Test

Capture of Supply Rail During Interruption Test with Additional Capacitor

Shown in the image below is the location where the additional 100 uF capacitor was added to the development board.

Interruption Test Setup PSoC Development Board with Capacitor

While this test is straightforward on simple hardware, it shows the basic process behind interruption testing.

Final Comments
This series of blog posts focused on an overall view of the hardware design for the power supply interruption tester. While not every aspect of the design process was covered in detail, design files have been provided in the Downloads section to assist those interested in producing a similar project.

Downloads
Listed below are the PSoC Creator project, Gerber and BOM files for the Interruption Tester project. This project is supplied as shown in this blog (Posts 1 to 5).

Display Schematic and BOM

Display Gerber and NC Drill

Driver Schematic and BOM

Driver Gerber and NC Drill

Rear Panel Gerber and NC Drill

PSoC Creator Project (Complete Archived)

PSoC Silicon ID Header File Creation

Summary
This blog offers a solution to generate PSoC header files from Cypress DAT files using PowerShell scripts. Available Cypress DAT files are merged and then converted into a single header file.

There is a thread similar to this post on the Infineon website called ‘JTAG/Silicon ID reference file’.

History
Fluctuations in global chip levels have resulted in a wider range of microcontrollers seen by companies responsible for programming and testing electronic hardware. 

To accommodate changes in microcontrollers using a more automated process for creating software header files, the scripts mentioned in this blog were designed. These scripts are fully functional, however, not without limitations as this is an initial foray into splitting scripts with this type of file content manipulation. 

The scripts were written in two parts because one script was made to run in the Program Files directory that contains the relevant DAT files. The second script was made to run with the merged DAT file.

Installation Requirement
To access the DAT files, the Cypress (Infineon) PSoC Programmer should be installed. The DAT files are located at the following location - C:\Program Files (x86)\Cypress\Programmer\Devices

Example of Cypress .DAT File Listing

The DAT files contain various items of PSoC information. Of this, the device name and ID range are of primary interest. 

As an example for PSoC device CY8C4125AZI-473, the entry from file CY8C4xxx.dat is displayed below.

2,CY8C4125AZI-473, CY8C4125AZI-473, 48, 32768, 3, 04_2B_11_93, 04_2B_12_93, v33

Whether the PSoC ID is utilised to program PSoC devices or other information such as the size of the flash is needed for programming file verification, the PowerShell script could easily be adapted to suit these purposes.

Implementation
The first script called 'dat_merger.ps1' combines multiple DAT files using the PowerShell add-content command. The script was designed to handle all DAT files in the Cypress Programmer Devices directory however the script will also work on a single DAT file. 

Additionally, the first row in each DAT file is removed since this is redundant. To process the file in the next script, the merged file is saved in CSV format.

$dir = Get-Location
Write-Host "Merging Files"

$source ="$dir\*.dat"
$destination = "$dir\merge.csv"

# Remove first row and merge all files in directory
Get-ChildItem -Filter '*.dat' | ForEach-Object {
Get-Content $_ | Select -Skip 1 | Add-Content $destination
}

The second script dat_parser.ps1 removes any unwanted columns, selects only the first column of PSoC IDs, adds the text ‘#define’, formats the ID into a preferred value by stripping the formatting and then saves the result as a jtag.h file.

$dir = Get-Location
Write-Host "Parsing files in $dir"
# Grab merged csv files
$source = "$dir\merge.csv"
$destination ="$dir\jtag.h"

# Strip columns, add hash define and number format for each line, strip CSV then save as header file
Import-CSV-Delim ','$source -Header a,b, c, d, e, f, g |
Select "b","g" |
ForEach-Object {$_."b" = "#define $($_."b")";$_} |
ForEach-Object {$_."g" = "0x$($_."g")";$_} |
ConvertTo-Csv -NoTypeInformation |
Select-Object -Skip 1 |
# Option for tab instead of spaces
#% { $_ -replace ‘_‘, “” -replace (‘,‘, "`t")  -replace ('"', '')} |
% { $_ -replace ‘_‘, “” -replace (‘,‘, ''.padleft(10, ' '))  -replace ('"','')} |
Out-File $destination -Encoding utf8

Output
The first script would merge DAT files. Two example files were chosen CY8C42xx-D.dat and CY8C44xx.dat.

Before Script 

1,CY8C42xx-D, CY8C42xx-D, 8, 5, 128
2,CY8C4245PVI-DS402, CY8C4245PVI-DS402, 28, 32768, 3, 17_03_11_A7, v17
2,CY8C4245FNI-DS402, CY8C4245FNI-DS402, 25, 32768, 3, 17_02_11_A7, v17
2,CY8C4246PVI-DS402, CY8C4246PVI-DS402, 28, 65536, 3, 17_01_11_A7, v17
2,CY8C4246FNI-DS402, CY8C4246FNI-DS402, 25, 65536, 3, 17_00_11_A7, v17

1,CY8C44xx, CY8C44xx, 8, 5, 128
2,CY8C4A45PVI-481, CY8C4A45PVI-481, 28, 32768, 3, 1C_02_11_AC, v17
2,CY8C4A45FNI-483, CY8C4A45FNI-483, 45, 32768, 3, 1C_03_11_AC, v17
2,CY8C4A45LQI-483, CY8C4A45LQI-483, 48, 32768, 3, 1C_00_11_AC, v17
2,CY8C4A45AZI-483, CY8C4A45AZI-483, 48, 32768, 3, 1C_01_11_AC, v17
2,CY8C4A45FNQ-483, CY8C4A45FNQ-483, 45, 32768, 3, 1C_41_11_AC, v17
2,CY8C4A45LQQ-483, CY8C4A45LQQ-483, 48, 32768, 3, 1C_40_11_AC, v17

After Script 

2,CY8C4245PVI-DS402, CY8C4245PVI-DS402, 28, 32768, 3, 17_03_11_A7, v17
2,CY8C4245FNI-DS402, CY8C4245FNI-DS402, 25, 32768, 3, 17_02_11_A7, v17
2,CY8C4246PVI-DS402, CY8C4246PVI-DS402, 28, 65536, 3, 17_01_11_A7, v17
2,CY8C4246FNI-DS402, CY8C4246FNI-DS402, 25, 65536, 3, 17_00_11_A7, v17
2,CY8C4A45PVI-481, CY8C4A45PVI-481, 28, 32768, 3, 1C_02_11_AC, v17
2,CY8C4A45FNI-483, CY8C4A45FNI-483, 45, 32768, 3, 1C_03_11_AC, v17
2,CY8C4A45LQI-483, CY8C4A45LQI-483, 48, 32768, 3, 1C_00_11_AC, v17
2,CY8C4A45AZI-483, CY8C4A45AZI-483, 48, 32768, 3, 1C_01_11_AC, v17
2,CY8C4A45FNQ-483, CY8C4A45FNQ-483, 45, 32768, 3, 1C_41_11_AC, v17
2,CY8C4A45LQQ-483, CY8C4A45LQQ-483, 48, 32768, 3, 1C_40_11_AC, v17

 

Running the second script on the merged file output from the first script results in a new file called jtag.h as shown below.

#define CY8C4245PVI-DS402         0x170311A7
#define CY8C4245FNI-DS402         0x170211A7
#define CY8C4246PVI-DS402         0x170111A7
#define CY8C4246FNI-DS402         0x170011A7
#define CY8C4A45PVI-481         0x1C0211AC
#define CY8C4A45FNI-483         0x1C0311AC
#define CY8C4A45LQI-483         0x1C0011AC
#define CY8C4A45AZI-483         0x1C0111AC
#define CY8C4A45FNQ-483         0x1C4111AC
#define CY8C4A45LQQ-483         0x1C4011AC

One of the limitations with the current implementation is the uneven padding between the PSoC device name and the ID. The parser code inserts ten white spaces which may not conform with all programming styles.

Final Thoughts
The PowerShell scripts (under GPL) have been tested on several DAT files however the outputs should be verified as part of standard practice. Improvements are welcomed!

Downloads
 

dat_merger.ps1

dat_parser.ps1

jtag.h
(Example of PSoC4, PSoC5)

 

Voltage Interruption Tester for IEC 61496-1 Part 4

Summary
This blog continues from part 3 of the supply voltage interruption tester (unit) post.

Covered in this blog are aspects of the Printed Circuit Board (PCB) implementation for the Infineon (Cypress) CapSense and output driver temperature measurements.
 
CapSense
CapSense has been available for over a decade however, I had not had a practical use for this technology on either a hobby or professional level until the interruption tester design. 

For the interruption tester, CapSense buttons were chosen instead of standard mechanical push buttons. During testing of the prototype interruption tester, daily variations in Capsense measurements were noted. While the variation resulted in sensitivity changes, tuning the CapSense component addressed most issues.

For the PCB layout, loosely following the CapSense PCB guidelines (Section 6.4) on a two-layer PCB resulted in poor performance. Tuning out interference or crosstalk was not achievable. This was likely due to the trace-to-trace spacing although the root cause was not investigated.

CapSense Trace-to-Trace Spacing - Courtesy Infineon

The design used in this blog uses a four-layer PCB with increased spacing between CapSense traces. For the 0.2 mm CapSense traces on the bottom layer, a 1.2 mm trace separation was used where practicable. Cross-channel triggering on CapSense lines no longer occured.

Interruption Tester - Radial Slider Trace-to-Trace Distance

Highlighted in the image below are the Capsense traces leading to the microcontroller for the radial slider.

Interruption Tester - Trace-to-Trace Spacing for Radial Slider

Output Driver Temperature Testing
For tests 1 to 3, the high-side drivers (IPS160H) were driven into a resistive load to create a load of approximately 2.4 A. Temperature measurements were taken of the high-side driver(s) active for that test.

The test conditions for the various test are shown below.

Setup for Tests 1 to 3
Supply 1: DC 24 V
Supply 2: DC 12 V
Load: 10 R (resistive)
Test duration: 30 min
Ambient Temperature: Between 18 °C to 20 °C

Test 1 Results
Channel 1 IPS driver: 48 °C
Channel 1 Diode: 70 °C

Test 2 Results
Channel 1 IPS driver: 49 °C
Channel 1 Diode: 72 °C
Channel 2 IPS driver: 35 °C
Channel 2 Diode: 35 °C

Test 3 Results
Channel 1 IPS driver: 50 °C
Channel 1 Diode: 72 °C
Channel 2 IPS driver: 34 °C
Channel 2 Diode: 34 °C

Driver Temperatures

Test 1 - IPS Driver Temperature

 

Test 1 - Diode Temperature

The captures for the tests 2 to 3 were similar to those shown above for test 1. For heat dissipation the output drivers were mounted on the bottom of the PCB. Thermally conductive silicone pads can be used to move heat into the aluminum case of the Interruption Tester.

Setup for Test 5
Supply 1: DC 12 V
Supply 2: DC 60 V
Load: Transorb
Test duration: 1 min
Ambient Temperature: 20 °C

For test 5, a surface mount Transorb of unknown voltage was tested by attaching by short wires to the Interruption Tester.

Test 5 - Temperature of Transorb Under Test

While the output drivers showed little signs of heating, the Transorb heating was excessive.

Test 5 - Waveform Measurement across Transorb

The existing test duration of 100 Hz was changed as a result of this test.

More in post five

Voltage Interruption Tester for IEC 61496-1 Part 3

Summary
This blog continues from part 2 of the supply voltage interruption tester (unit) post.

Covered in this blog is an overview of the unit assembly and code functionality.

Unit Assembly
The display printed circuit board (PCB) contains a display (LCD) that requires mounting. The associated LCD hardware consists of M2.5 bolts, washers and spacers.

Interruption Tester Mounted LCD

For the connection between the display and power PCBs, surface mount connectors were used. Due to global supply constraints, this connector pair will be changed on a future PCB revision.

For the complete unit assembly, an anodised metal enclosure (Multicomp Pro MC002177) was utilised. The front and power PCB are fitted via the surface mount connectors and then slid into the enclosure. PCB slots are provided at various heights on the inside walls of the enclosure. To mount the front panel PCB, six bolts are required.

Interruption Tester Front Panel

The rear panel is placed over the banana connectors and held in place with a further six bolts.

Interruption Tester Rear Panel

Rubber feet were fitted to complete the assembly.

Code Summary
The Infineon (Cypress) PSoC project is a standalone application targeted at the device CY8C4245AXI-483. The roadmap for the Interruption Tester project contains a firmware change to use the PSoC bootloader to suit field upgrades.

The project code is broken into three sections which relate to the user interface buttons, LCD and output drivers. These handlers interface with PSoC digital blocks by way of a system timer, Capsense, LCD, PWM and other interfaces.

PSoC Capsense Component

 

For the Capsense button handler, the 5-element radial Capsense (slider) value is processed which allows the selection of the LCD menu item.
The On/Off (Output) button is processed through a state machine that performs a latching/unlatching action on the button press. 
 

Capsense Scan Configuration

When the output is Off, the LCD presents a test number, that relates to the pre-programmed tests detailed in the following section. 

While the output is activated (On), the selection of other tests is not possible. The PWM blocks are programmed for continuous operations.

The display handler uses details from the button handler for the management of display strings.

PSoC LCD Component

The LCD has other tasks such as throwing up the boot screen or error states when applicable.

The output handler uses details from the button handler to configure PWM, configure the multiplexers and activate the high-side drivers. The two high-side drivers individually switch two input voltages, Voltage 1 (V1) and Voltage 2 (V2).

PSoC PWM and Multiplexer Components for Output Stage

Summary of Programmed Tests
Five tests are programmed with each test summarised below.

The term dipping, as described in the IEC standard, refers to the power supply changing voltage compared to interrupting which refers to the power supply switching OFF.

Test 1 - 10 ms pulse width interrupting Voltage 1 (V1) at a frequency of 10 Hz.  Voltage 1 is switched OFF.

Interruption Tester - Test 1 Output No Load

Test 2 - 20 ms pulse width dipping Voltage 1 (V1) at a frequency of 5Hz.  Voltage 1 is switched OFF and Voltage 2 will be supplied during V1 off time.

Interruption Tester - Test 2 Output No Load

Test 3 - 500 ms pulse width dipping in Voltage 1 (V1) at a frequency of 0.2 Hz.  Voltage 1 is switched OFF and Voltage 2 will be supplied during V1 off time.

Interruption Tester - Test 3 Output No Load

Test 4 – 1.8 ms pulse width dips in Voltage 1 (V1) at a frequency of 50 Hz. Voltage 1 is switched OFF.

Interruption Tester - Test 4 Output No Load

Test 5 – Approximately 280 us pulse width (spikes) at a frequency of 100 Hz. Voltage 1 remains ON and Voltage 2 will be switched ON to generate the spike.

Interruption Tester - Test 5 Output No Load

The IEC standard states that the equipment under test (EUT) should be subject to ten dips. Updates to the code could allow for the dips to be limited to ten. The tests currently continue to run.

Tests 1 through 3 allow for basic testing to the IEC standard.

Test 4 was created for verifying filters targeting 50 Hz.

Test 5 can be used with an oscilloscope to check the performance of devices and designs using protection diodes. These diodes may include steering or Transient (Tranzorbs) diodes. A narrow pulse (spike) is applied for a short time at a frequency of 100 Hz. The frequency may need to be adjusted for applications where the protection diodes are low power.

Tests 1 and 2 are classified as B tests meaning that the operation of the EUT should not be changed as a result of the test. Test 3 is classified as a C-test which means that the EUT can fail in a known condition.

More in post four

Voltage Interruption Tester for IEC 61496-1 Part 2

Summary
This blog follows a previous post where the concept for a supply voltage interruption tester (unit) was validated.

In this blog, the design was formalised by implementing the design on circuit boards using available electronic components. The alternate design supports operating voltages from DC 8 V to 60 V at 2.5 A.

Voltage Interruption Tester Prototype

The design goal was to create a cost-effective unit that would provide indicative testing for Section 4.3.2.2 Supply Voltage Interruptions of the standard IEC 61496-1. The testing is indicative because this units is not an IEC qualified unit.

Two external power supplies supply the voltages that are switched by the unit to generate the required output waveforms.

In addition to the standard IEC tests, two additional tests were added; one for generating repetitive mains frequency noise (50 Hz) and the second for testing diodes such as Transient (TVS).

Example Output Waveform from Voltage Interruption Tester

Editing the project source could yield additional or completely new tests.

Hardware Overview
Three circuit boards (PCB) were created. These consisted of a front, rear and internal PCB. For ease of use on the bench, the design was made to suit a small aluminium enclosure. The two boards containing electronic devices detailed below.

Power PCB Prototype (Top Side)

The first board, labelled the power board, contained a DC 3.3V regulator with an operating range of DC 4 to 60 V, high side drivers, pluggable power banana connectors and an optional USB interface. The high side driver operating voltage is DC 8 to 60V.

Power PCB Prototype (Bottom Side)

The front PCB was also purposed as the unit's panel. This board contained a Cypress microcontroller and a two-line LCD.

Display PCB Prototype (Bottom Side)

Buttons were implemented on the PCB using the Cypress Capsense interface.

Display PCB Prototype (Top Side)

Power PCB
The power PCB was created as a double-sided board so that the two high side switches (IPS160H) could take advantage of heat dissipation to the aluminium case if needed. Signals from the high-side switches were provided to the microcontroller although monitoring was not implemented at this time.

PCB mount banana plugs provided the connections for the dual supply inputs and voltage interruption tester output.

Powering of the microcontroller and LCD on the display PCB was realised using a DC 3.3 V wide operating range DC-DC switchmode (LMR16006XD). The switchmode will begin operating with an input voltage of 3.6 V which may be useful for high side switches with a lower operating voltage.

Debug and diagnostic feedback were provided through an optional USB interface.

A resistor population option allows for the selection of the switchmode supply source. This could either be input voltage 1, 2 or the optional USB.

Display PCB
Contained on the display PCB were the microcontroller and two-line LCD.

Prototype Supply Interruption Tester LCD

An interface for the operator was achieved using PSoC Capsense buttons. Capsense signals were interfaced to the Cypress microcontroller providing a five-element radial slider and an On/Off button. The cross-hatching pattern seen on the PCB significantly helps with the Capsense operation.

Rear PCB
There were no components mounted on the rear PCB however the front and rear PCBs used the silkscreen to provide the relevant operational information.

 

Rear PCB Prototype

  

Continued in Part 3