Saturday, 14 April 2018

PSoC 4 Bootloader UDB vs SCB Speeds

Summary
This purpose of this blog was to test and verify, partially for my own curiosity, the download speeds of I2C, UART and UART operating as RS485 for the PSoC 4 using UDB and SCB type components. Operating the SCB UART in RS485 was not possible as an out of box setup, so this test was omitted.

Test Hardware
A Cypress PSoC development kit CY8CKIT-042 was configured to use the on-board I2C, UART or UART (RS485) using UDB and SCB components.

CY8CKIT-042
CY8CKIT-042 - Courtesy Cypress Semiconductor

For UART testing, a separate USB to Serial converter by 
Prolific was utilised. The model from Adafruit for instance was USB to TTL Serial Cable - Debug / Console Cable for Raspberry Pi. For connecting the TTL end of the Prolific cable, the Black wire was connected to 0V, White to pin P0.5 and Green to pin P0.4 of the Cypress Development Kit.


Prolific USB to TLL Converter
Prolific USB to TLL Converter

Similarly a USB to RS485 converter by FTDI was used in conjunction with a LinkSprite RS485 Rev1 adaptor board to connect between the target PC and the Cypress development board. Some hardware modifications were required on the earlier model LinkSprite for use with the Cypress Development board. These changes were related to the Receive and Transmit Enable lines which needed to be driven from the PSoC using the UDB components TX Enable output. The following link LinkSprite RS485.pdf, shows the modifications made to the LinkSprite Rev 1 board.

FTDI USB-RS485-WE-1800-BT
FTDI USB-RS485-WE-1800-BT

LinkSprite (RS485) Fitted to PSoC Development Board
LinkSprite (RS485) Fitted to PSoC Development Board

From the FTDI RS485 adaptor to the LinkSprite only the Data+ and Data- connections were used, which corresponds to the Orange and Yellow wires, as shown in the image above.

Test Software
An application for the DS18B20 OneWire bus was converted into a bootloadable project for testing. Any project could have been used, this was handy at the time. It should be noted that the programming file .CYACD used for testing was less than 20kb.

As mentioned in the blog introduction, both UDB and SCB communications solutions were tested. Where possible the Cypress project and components were left with minimal changes. Clocks with fractional dividers were used to achieve the best tolerance for the communications rates. Note that other methods of deriving the most desirable clock for the given baud rate were not tried - only minimal changes were made to the project.

Some notes on the testing performed.

Reference Download I2C
In most instances, when using a 042 Cypress Development Kit, the Kitprog hardware interface is used to update the target PSoC device from PSoC Creator. The time to perform an update could be determined from PSoC Creator although it would be unlikely that a field solution would use a Kitprog interface for updating the PSoC. I2C was therefore used as the reference for download speeds on this development kit.

Cypress Windows Bootloader Host
For all of the downloads performed, the Cypress Bootloader Host was used from within PSoC Creator. The Cypress UART Bootloader application does not support baud rates above 115200 at the time of writing.


Cypress Bootloader Host
Cypress Bootloader Host
Baud Rate Clocks (SCB)
The clocks shown below were used for UART testing, with the oversampling setting left at the default of 12, for a range from 57,600 to 921600 baud. This was implemented due to the warning raised by PSoC Creator relating to clock accuracy. All rates below 57,600 did not show a warning relating to tolerance.


PSoC Creator Clock Tolerance Warning
PSoC Creator Clock Tolerance Warning


SCB UART 56,700 Clock Input
SCB UART 56,700 Clock Input


SCB UART 115,200 Clock Input
SCB UART 115,200 Clock Input


SCB UART 230,400 Clock Input
SCB UART 230,400 Clock Input
SCB UART 460,800 Clock Input
SCB UART 460,800 Clock Input
SCB UART 921,600 Clock Input
SCB UART 921,600 Clock Input
Baud Rate Clocks (UDB)
The clocks shown below were used for UART testing from 460,800 to 921600 baud. All rates below 460,800 did not show a tolerance warning.


UDB UART 460,800 Clock Input
UDB UART 460,800 Clock Input
UDB UART 921,600 Clock Input
UDB UART 921,600 Clock Input

I2C Configuration
For the I2C (not EZI2C) the data rates were changed from 50 to 1000kbps in the PSoC Creator component.


PSoC Creator I2C Component Bootloader Configuration
PSoC Creator I2C Component Bootloader Configuration
A corresponding change was made to the Bootloader Host application to match the data rate - example capture of the 1000kbps shown below..


PSoC Creator Bootloader Host I2C 1000kbps
PSoC Creator Bootloader Host I2C 1000kbps
UART Configuration
The UART was configured in the same manner for the UDB and SCB components with the exception of the RS485 TX Enable line which is not available on the SCB component for the PSoC4.


UART SCB Component Basic Configuration
UART SCB Component Basic Configuration
UART SCB Component Advanced Configuration
UART SCB Component Advanced Configuration
The oversampling setting was unchanged at 12 and the Tx and Rx buffer were configured for 64 bytes as required for the Bootloader component.


UART UDB Component Configuration
UART UDB Component Configuration
UART UDB Component Advanced Configuration
UART UDB Component Advanced Configuration
For the UDB component the Tx and Rx buffer were configured for 64 bytes as required for the Bootloader component. When required, the hardware TX Enable output was enable in the UDB component.

Test Results
After all the setup detail above, the results recorded from the Cypress Bootloader application with a PSoC 4 are listed in the table below.


Cypress Bootloader Download Times for UDB and SCB Components
Cypress Bootloader Download Times for UDB and SCB Components
The same tests were conducted several times and it should be noted that there was some variation in the results. As a percentage the variation was no more than five percent.

Graphing the recorded results listed above, the shortest time for download is easily visible, the SCB UART. Coming in a close second is the I2C connection seen on most Cypress development kits. The results do show how dedicated hardware on the PSoC 4 performs notably better than Universal Digital Blocks (UDB).


Graphed Cypress Bootloader Download Times for UDB and SCB Components
Graphed Cypress Bootloader Download Times for UDB and SCB Components
Code and Project
The code snippet for the Bootloader application is listed below.

/* ========================================
 *  Shell code for running the bootloader
 * ========================================
*/

#include "project.h"

int main(void)
{
    CyGlobalIntEnable;      /* Enable global interrupts. */   
    Bootloader_Start();     /* Start bootloader, wait forever */

    for(;;)
    {
    }
}

/* [] END OF FILE */ 

Lastly the project itself which contains the Bootloader and Bootloadable applications.


Bootloader - Bootloadable Test Application
Bootloader - Bootloadable Test Application




Wednesday, 11 April 2018

Build Number for PSoC Creator Projects - Post Build

Summary
Recently during development of a PSoC based project there was a requirement to use an automatic incrementing build number. This blog provides an example project with incrementing build number using command line scripting.

The use of a build number may be considered trivial by some and certainly with the use of revision control software such as Veracity, SourceGear's Vault or Fossil this is most likely the case. There are however situations where applying revision control consumes more time and resources than necessary. Providing a programming file, which can be identifiable, can remain a suitable solution for a software developer.

Test Hardware
In order to test the incrementing build number using PSoC Creator, hardware was not compulsory. For demonstration an example project was based around the Cypress PSoC development kit CY8CKIT-042.

CY8CKIT-042
CY8CKIT-042 - Courtesy Cypress Semiconductor

Script
While searching online for a suitable script, I came across a thread on Stack Overflow from user ansgar-wiechers. The example script he listed, which can be seen on StackOverflow, served as a basis for the PSoC Creator script.

So what does this script do.... firstly it looks for a file called buildnumber.h in the PSoC Creator project path. Next, the contents of the header file is searched until the string BuildNumber= is found. Then the integer following the equals sign is incremented by one. The original file, with an updated build number, is then saved back to the original buildnumber.h file.

As can be seen in the script below, there are no checks, no limits, so programmer beware!

Set fso = CreateObject("Scripting.FileSystemObject")

Set re  = New RegExp

re.Global = True


Function IncMaint(m, g1, g2, pos, src)

  IncMaint = g1 & (CInt(g2)+1)

End Function


ProjectMainFolder=fso.GetAbsolutePathName(".")

WScript.Echo ("Build number: Incrementing the build number located at:" & ProjectMainFolder)

rcfile = ProjectMainFolder & "\buildnumber.h"

WScript.Echo(rcfile)

rctext = fso.OpenTextFile(rcfile).ReadAll

re.Pattern = "((?:BuildNumber) )(\d+)"

rctext = re.Replace(rctext, GetRef("IncMaint"))

re.Pattern = "((?:BuildNumber)= )(\d+)"

rctext = re.Replace(rctext, GetRef("IncMaint"))

fso.OpenTextFile(rcfile, 2).Write rctext


Build Number Header File
In the file containing the build number the project major and minor revisions were also included.

/****************************************************************************
* buildnumber.h
*
* Example header file to show usage of BuildNumber keyword and equals signal
*
* The text BuildNumber= can be anywhere in this file
*
*****************************************************************************/
#include "project.h"
const uint8_t MajorRev= 1;
const uint8_t MinorRev= 1;
const uint8_t BuildNumber= 1;

PSoC Creator - Post Build Command
A call is made to the external VBS file under the PSoC Creator menu, Project, Build Settings using User Commands. It should be noted that for the example shown the script was contained in its own folder Scripts and not attached to the PSoC Creator project.


PSoC Creator Post Build Script - Increment Build Number
PSoC Creator Post Build Script - Increment Build Number
Shown in the capture below is the the Post Build command to call the VBScriptcscript ${ProjectDir}\Scripts\buildnumber.vbs


PSoC Creator Post Build CScript Call
PSoC Creator Post Build CScript Call
For this example project the Post Build was used. Depending on the requirement Pre Build may be needed.

PSoC - Build Number Usage
For the PSoC Creator project, the header file containing the build number is accessed in the usual manner using #include "buildnumber.h". For the example project the include was in main.c and the revision and build numbers were written to the serial port.

/****************************************************************************
* Build Number Example
*
* Uses a Visual Basic Script to find an increment 
* the integer associated with the variable BuildNumber

* The script is called as a post-compiler command in
* the Project -> Build Settings menu
*
* Code implementation is a skeleton to illustrate usage of the script, error checking should be implemented

* Credit to https://stackoverflow.com/users/1630171/ansgar-wiechers
* for ideas on the implementaion as mentioned on the following
* blog https://stackoverflow.com/questions/19891195/how-to-increment-values-in-resourse-file-by-using-vbscript
*
******************************************************/

#include "project.h"
#include "stdio.h"
#include "buildnumber.h"
char Version_Char[8];
int main(void)
{
    CyGlobalIntEnable; /* Enable global interrupts. */
    UART_Start();
    sprintf(Version_Char, "Version %d.%02d build %03d\r\n", MajorRev, MinorRev, BuildNumber);
    UART_UartPutString(Version_Char);
    for(;;)
    {
    }
/* [] END OF FILE */

Compiling PSoC Creator
When compiling a project, with the script below added to the Post Build command, a message is echoed from the script to indicate that the Build Number is being incremented.

cscript .\Scripts\buildnumber.vbs
Microsoft (R) Windows Script Host Version 5.812
Copyright (C) Microsoft Corporation. All rights reserved.
Build number: Incrementing just the build located at:C:\...\UART_Example\UART_BuildNumber.cyds

UART Debug
Compiling the example project under PSoC Creator with the major, minor, build number set to 1.1.0, then programming the PSoC development board yields the screen capture below from TeraTerm.


Auto Incrementing Build Number Tera Term Debug
Auto Incrementing Build Number Tera Term Debug
Compiling the project again and programming the development board yields the capture below showing the increment in build number.


Auto Incrementing Build Number Tera Term Debug
Auto Incrementing Build Number Tera Term Debug

Example PSoC Creator Project
The example PSoC Creator 4.1 project and VBScript are available to download below. For comments or bugs leave a comment below, enjoy!


Increment Build Number Example Application PSoC Creator 4.1
Increment Build Number Example Application PSoC Creator 4.1


Increment Build Number Example VB Script
Increment Build Number Example Script

Sunday, 1 April 2018

PCB vias solder mask tenting

Summary
This blog highlights some of the implications for PCB 'board' loaders during the reflow or wave soldering process when Printed Circuit Board (PCB) designers choose not to tent solder side vias.

PCB Manufacturer Tenting Limitations
With the advent of higher density devices such as microcontrollers with configurable logic, Field Programmable Gate Arrays (FPGA), System On Module (SOM), System On Chip (SOC) and high power FET drivers becoming more prevalent in commercial equipment and hobbyist designs, there comes a requirement to manage exposed pads and vias beneath these devices. 

In some instances high density components may have an exposed pad that require a connection utilising vias for a variety of reasons. The exposed pad may serve as electrical connection, such as an input power supply, output in the case of a switch mode regulator, the pad may be used for PCB mounting by providing bonding strength (due to the ever decreasing component footprint) or for heatsinking, by acting as a thermal pad such is the case for high power FET drivers.

In the image below are a few examples of different sized vias which have been used for different reasons on the same PCB.


Tented and Untented Vias
Tented and Untented Vias
Identified in the red box are vias which are used for standard TTL signal connections. The via hole size is 0.3mm. Vias with this hole size are commonly tented during the PCB manufacturing process using solder resist, unless they have been earmarked for alternative purposes such as test points, probing, programming or other similar purposes.

Shown in the light blue box are larger vias with a 0.7mm hole which are used for connections to the PCB internal power planes. Vias of this size are tented where possible unless there is a good reason not to do so or the PCB manufacturer is unable to mask to this via size. Reasons for not tenting may include thermal connections to exposed pads or a need to increase the current handling capacity of the via. Both of these reasons may require solder or a 'plug' to fill the via.

The purple box shows a cluster of untented vias with a 0.5mm hole. These vias reside below a microcontroller featuring an exposed pad. The vias on both sides of the board are not tented although these vias are usually tented on the solder (non-component) side of the PCB.

Lastly shown in the yellow box is an array of vias with a 0.381mm hole. The grouped formation of vias is commonly termed 'stitching' in software packages such as Altium Designer. For this design the top and bottom copper layer represent the ground plane which are stitched together using multiple vias. Vias of this size and smaller are usually always tented.

For the example board shown, almost all of the vias are listed as tented in the PCB file and the Gerber files. Clearly not all the vias appear to be tented in a thick solder mask. The reason for the discrepancy can lie with the capability of the PCB manufacturer. Not all PCB manufacturers detail their limits for tenting vias with solder mask or are able to open the latest PCB files from software packages such as Altium Designer (a good reason why Gerbers are used in the industry). This issue can be remedied to some degree by supplying the Gerber files to the manufacturer, in the format requested, and then asking to verify the machine Gerber files that the manufacturer intend on using in their PCB production equipment.

PCB designers should be mindful however that even the final Gerber files supplied by the PCB manufacturer may not always be what is actually produced. For example, mutlilayer boards with power planes to the edge of the board will have, in general, a 'pullback' rule applied to that layer even if the PCB does not have a pullback rule. To prevent these rules from being applied by the PCB manufacturer comments or notations should be explicitly noted on the PCB file or Gerber file as 'no pullback on this layer'. Somewhat off topic although this concept also applies indirectly to vias and solder mask.

With regards to the maximum size of via which can be covered with solder mask, for a standard manufacturer a 0.8mm hole may be too large where for the more experienced or better tooled manufacturer, a 1.2mm hole may be considered the upper limit. Asking the manufacturer will at least provide an idea of their manufacturing capability. This information can then be included in the PCB design file for the PCB manufacturer.

Via Placement and Tenting Issues
A single untented via rarely causes placement or issues for the PCB loader. The word rarely is used with caution however because a single, poorly placed via, without tenting can cause issues when located too close to another surface mount component, to the pad of a PCB mount metalised connector or the under the metal body of a mechanical component such as a HDMI connector.

The image below shows vias with an equidistant spacing of 1.1mm connected to a component with an exposed pad on the opposite side of the PCB. A via spacing down to 0.5mm should usually not cause a problem for the PCB loader whether the soldering process is reflow, as shown below, or solder wave.


Via Spacing
Via Spacing
Shown in the subsequent image is a higher density via placement with a spacing of 0.8mm. Due to the increased number of untended vias and possibly solder paste, the solder readily flows from the top side of the board to the bottom during the reflow process.


Higher Density Via Spacing
Higher Density Via Spacing
Although the protruding solder could easily be removed as part of the post manufacturing process, this additional work can increase the final PCB cost and is best avoided during PCB design by tenting the vias. It should also be noted that the solder protruding from the vias may not be excess solder but instead solder that should be between the exposed pad of the component and the copper pad of the PCB.

No Via Tenting
Where vias are used for other purposes, such as ground planes or heatsinking, the PCB designer has the option to leave the via with no tenting. During the PCB population process solder may fill the vias, although using solder to fill vias in this manner is not a guaranteed process. The image below shows the via arrangement under a high current switch where not all of the vias have been filled with solder.

Staggered Via Layout Connected to Polygon
Staggered Via Layout Connected to Polygon
The subsequent image shows the component side of the board without the physical component fitted.


Staggered Via Layout Component Side
Staggered Via Layout Component Side
Via Tenting
Although this blog focuses on vias without tenting, it should be noted and sighted in the image below, that even vias with a 1mm hole can be tented with solder mask by a sufficiently qualified PCB manufacturer.


Tented Vias Connected to Polygon
Tented Vias Connected to Polygon
Design Suggestions
Knowing the limitations of the PCB manufacturer and the PCB loaders soldering process would allow ideal selections to be made during the PCB design process.

This comment is idealistic, not realistic. 

More often than not people utilise online PCB manufacturers which do not fully disclose the capability of their PCB manufacturing equipment. Additionally the PCB manufacturer's website may be a PCB broker that farms large groups of common layer boards to the most suitable PCB manufacturer at that time.

With this in mind, the suggestions below for tenting and spacing, of through PCB vias, are for a typical PCB manufacturer and largely depend of the via size and use.

Max via hole size for tenting: 1.2mm
Min via to via land separation for untented vias: 0.3mm
Min via to via land separation for tented vias: 0.15mm

Tented Vias Connected on Multiple Polygons
Tented Vias Connected on Multiple Polygons